Dear readers, if I want to reset an NE555 timer (by pushing a button within a time frame) at the point where the output signal is at the end of the high voltage as highlighted in the diagram. How can I accomplish this?


Thank you for reading and have a nice weekend

 

A push-to-make pushbutton connecting reset to ground will reset the 555. The reset pin will need to be tied high with a resistor to hold reset high when the button is not pressed.

Is the diagram you provide a scope of the 555 output? If so, it seems that you want to reset the 555 just as the time period ends and the 555 performs a reset anyway.

 

A push-to-make pushbutton connecting reset to ground will reset the 555. The reset pin will need to be tied high with a resistor to hold reset high when the button is not pressed.

Is the diagram you provide a scope of the 555 output? If so, it seems that you want to reset the 555 just as the time period ends and the 555 performs a reset anyway.

Yes sir It is in astable mode NE555. I want to reset the 555 just as the time period ends when i push a button I want to accomplish this using hardware design although microcontroller would be easy for this job

 

I don’t quite understand what you are trying to do.
The 555-timer circuit resets itself at the time you indicated in blue.

 

.... reset the 555 just as the time period ends when i push a button ....

When the time period ends the 555 will reset itself without any attention from you, as I said earlier.

Can you explain what you want to achieve by pushing a button at that time?

 

Perhaps he wants to stop the oscillator at the end of the next period after a button push, i.e. hold it in reset after that point.

 

A quirk when resetting the 555 is that it will pull the timing capacitor voltage to zero volts, not the 1/3Vcc that it normally goes to when oscillating, so the first half of the oscillation cycle after restart will be longer than the rest.

If that's a problem, you can use a diode with a voltage divider to prevent the voltage from going below 1/3Vcc when reset.
That will make the first cycle time after reset quite close to subsequent cycles.

Edit: Below is the LTspice simulation of a 555 astable circuit with first-cycle compensation, and an Enable input that uses a CMOS OR gate to stop the oscillation at the end of the complete last high cycle, regardless of when the Enable signal went low.

In the simulation below, notice that when the PB is pressed (yellow trace) and the Enable input (blue trace) goes low before the end of the Output high cycle (green trace), the 555 RST signal (red trace) doesn't go low (reset condition) until the Output goes low, thus the output pulse isn't truncated.

The oscillation then restarts when the Enable signal goes back high, with only a small difference in the first cycle period as compared to the following cycles.
For comparison, at the bottom is a thumbnail of the simulation without the compensation, if a long first-cycle is not an issue.

Do either of those do what you want?