So I've been working on updating a couple old circuit board designs to make use of SMT parts etc., and I'm almost to the point of being ready to find a board house that can make me a couple PCBs (open to recommendations to where I can send off the gerbers etc.)

Anyway, I just wanted to know what is the proper size for the bypass caps normally placed adjacent to ICs... I thought 0.1uF was the norm, but all the bypass caps on this logic board are 0.01uF? (as in marked '103' vs. '104')

 

I normally use 0.1 MLCC for general digital bypassing and add a 0.01 COG in parallel around higher frequency stuff.

I've used JLCPCB and Oshpark for tons of small simple boards made with the auto gerber function from Eagle 9.

With matching options for finish the cheaper (top jlcpcb, bottom oshpark) boards are pretty good.

 

hi mm,
Look thru this PDF.
E

 

99.999 % of the time, 10 nf or 100 nf will make no difference to the baord.

 

Anyway, I just wanted to know what is the proper size for the bypass caps normally placed adjacent to ICs... I thought 0.1uF was the norm, but all the bypass caps on this logic board are 0.01uF? (as in marked '103' vs. '104')

The smaller caps are better at bypassing higher frequency noise and are often used with 0.1uF ceramic caps and larger electrolyticc/tantalum caps.

 

The highest frequency on these boards is 1MHz - the main system clock, so I'm inclined to go with 0.1uF caps.

 

Your sweating the small stuff,
just put 10 nf or 100 nf down ,
you will not notice the difference,

 

Not necessarily sweating it, just wanting to go with best practice / cost savings.

 

I'm just a noob/hobbyist so don't take my word for it, but ...

Is that 1MHz clock a square wave? There is a rule of thumb that says the signal band width = 0.35 / rise time. So the highest frequency of interest would depend on the edge speed of the clock signal (if it is indeed a square wave).

 

@hrs,
yes your right about the 0.35 rule of thumb,
but that's normally used for termination,

this is decoupling,
which is different, the "signal" is basically DC,
the decoupling is to supply the local current to the chip , to compensate for the voltage drop on the supply due to the RLC of the power system.

Your right, as frequencies go up, the glitch on the power supply can be worse, but its a second or third level effect.