Hi dears, I have just a couple of questions.

1)I am making a little circuit where I am using a presettable synchronous counter with asynchronous load
I know that is possible to load the PE input with an RC to generate a positive going transition, however someone told me to use a Schmit trigger gate to do that, and I am not so disappointed about it.
But, I always known that is possible to use an RC, with a low reasisteance and high capacitance value. For example: 1K and 1uF.
Is the RC really unsafe for this purpose?

2) I have to make a 3 input NAND gate with three NPN. I can work with a 40193 or a 74HC193.
It is better I choose different transistors depending on the IC I am using?

I have BC337 and BC547 in my drawer.. I am thinking to use BC337..
Consider I still don't have strong knowledge about transistors.

What do you suggest about my questions?
Thank you for your time

Simo

 

How wide (time) do you want your preset pulse to be?

 

How wide (time) do you want your preset pulse to be?

The sufficient time to activate it when power is supplied.
I thinked about 1ms, but also a 1us if is not too short. What do you suggest about it?
Then I will reactivate it with the NAND gate at the sequence 111.

Thank you.

 

Is this homework?

 

It's a little project which I am working on.

 

I think you need something like this. I used a 191 instead of a 193, because I didn't have a spice subcircuit for a 193.
The actual time constant of the preset delay is dependent on the risetime of vcc in your circuit.
I am including the .ASC file, in case anyone wants to run the simulation.

 

Hi Ron thank you for your reply.
The load time delay as we can see from the 74HC193 datasheet is from a minimum of 20ns to a typical 7ns with 5Vcc supply. Probably a lower value than 100k & 100nF for a shorter RC time charge is considerable? Please correct me if I am talking nonsense, probably I am missing some detail..

However, instead of 74HC14, seems I can use a 741G17, wich is a single schmitt trigger buffer, 7400 serie which is compatible with 74HC serie; seems to be perfect.

I would like attach (in the next message) a little scheme of the NAND transistor gate I would like to implement. If you will spend a few time to give me one more suggestion about it I will appreciate it very much.

Thank you for your clarifications & help.
Regard,
Simon

 

Hi Ron thank you for your reply.
The load time delay as we can see from the 74HC193 datasheet is from a minimum of 20ns to a typical 7ns with 5Vcc supply. Probably a lower value than 100k & 100nF for a shorter RC time charge is considerable? Please correct me if I am talking nonsense, probably I am missing some detail..

However, instead of 74HC14, seems I can use a 741G17, wich is a single schmitt trigger buffer, 7400 serie which is compatible with 74HC serie; seems to be perfect.

I would like attach (in the next message) a little scheme of the NAND transistor gate I would like to implement. If you will spend a few time to give me one more suggestion about it I will appreciate it very much.

Thank you for your clarifications & help.
Regard,
Simon

Load time delay is pretty much irrelevant. Your RC time constant needs to be long enough to hold the preset low until vcc has settled.
You can certainly use a single Schmitt trigger.
I'm not sure where you are going to use a 3 input NAND. My design has a 3 input AND gate. I suppose you could add a discrete or integrated inverter.
Again, I ask:

Why do you want to use a gate made of discrete transistors?

 

Load time delay is pretty much irrelevant. Your RC time constant needs to be long enough to hold the preset low until vcc has settled.
You can certainly use a single Schmitt trigger.

Ok.

Why do you want to use a gate made of discrete transistors?

Just because I am learning transistors. It's personal study. Maybe you are thinking I am crazy, however, probably I will not use it but I am interested about your judgment as you know more than me about it.

I attached two schemes images:
#1 - NAND NPN transistors
#2 - connection between the 74HC10 NAND gate, the schmit trigger buffer and the LOAD output.

Refearring to the scheme #2, due to the schmitt trigger is not an inverter the connection changes a little bit respect the example you attached before, so I thought to connect the NAND gate straight between the Schmitt trigger output, because I think it should work like a pull-up connection, if I am not making any mistake: after the trigger output is high, sequence 001 will be in output from the counter. As the NAND gate take this first three bits, NAND output will be high. When sequence 111 is out from the counter, NAND output will be down for a very short time.
Please correct me if my idea is wrong.

PS: I made the schemes with fidocad, wich is a simple free open source java based "circuit scheme editor" easy to use, but not an electronics simulator.
Every circuit can be edited through a .fcd extension file, which is the very circuit file, you can open and edit it with fidocad, or also with a text editor (but you will do nothing with it).
I leave a link to sourceforge fidocad download page if anyone is interested to try it. I also attached a zip file with the .fcd files if you (or anyone interested in this topic) want to change it and report your corrections if it needed.

Again, thank you so much for your time.
Regards,
Simo

 

Your logic looks OK, but the 74LVC1G17 does not have an open drain. It has an active pullup. Therefore, you can't pull its output down with a another device, such as your discrete NAND gate. If you try to, one or both devices may overheat and be destroyed.
The connection of two or more gate outputs is called wired OR. Each output must be either open drain (open collector if using BJTs), or must have tri-state outputs. 74HC10 cannot be wire-ORed, because it also has an active pullup. You may have to do some Googling if you don't understand these terms.

You can use an inverting Schmitt trigger with a discrete inverter after it. See below.
I simulated it. It seems to work.

 

Your logic looks OK, but the 74LVC1G17 does not have an open drain...

I always had a little dubt about if it should work or not. I didn't know this detail and you have been very clear. Thank you.

However, looking for devices of the 7400 series in wiki page, seems there are many with schmitt trigger input. I don't know the concept of how it is needed, but I will look forward for it.

I like your solution, (that's confirm that I am not so crazy trying I to use them ), I also think that without NPN just with logic gates, one solutions is as I attacched to the post.

Do you confirm?

However seems single gates are availables only in smd size.. I would like a common size like 555 etc.. They doesn't exist?
If not, I will use transistor. Why did you use 2n3904 NPN? BC337 are not good for this purpose?

Again, thank you, i learnt something new today .
Regards
Simo

 

I always had a little dubt about if it should work or not. I didn't know this detail and you have been very clear. Thank you.

However, looking for devices of the 7400 series in wiki page, seems there are many with schmitt trigger input. I don't know the concept of how it is needed, but I will look forward for it.

I like your solution, (that's confirm that I am not so crazy trying I to use them ), I also think that without NPN just with logic gates, one solutions is as I attacched to the post.

Do you confirm?

No. Both inputs of your NAND gate are normally low. Each input inhibits the other one.

However seems single gates are availables only in smd size.. I would like a common size.. They doesn't exist?

No, they don't.

If not, I will use transistor. Why did you use 2n3904 NPN? BC337 are not good for this purpose?

Again, thank you, i learnt something new today .
Regards
Simo

BC337 is fine.

 

And what about a pull-down connection as the scheme I attacched?

As the the power is supply, LOAD is already charged and after that a positive signal is supplied by the NAND gate.
Should work, or not? I tried with simulator and it seems ok..
I tried with an open collector output NAND and it doesn't works.

 

And what about a pull-down connection as the scheme I attacched?

As the the power is supply, LOAD is already charged and after that a positive signal is supplied by the NAND gate.

No! The resistor to GND on the NAND gate input forces the output high, regardless of what the other input is.

 

Hi, sorry for the late reply.

You have reason off course, I did it in a hurry so the result was certainly a fail.

But If I can use transistor for a NAND gate, I thought about implementing a schmitt trigger buffer with a single OP AMP, output to a PNP with collector connected to the NAND transistors output between a resisteance .

In simulation works fine. However, I am not experienced with schmitt trigger implementation.. I am looking forward to make me sure about the resistances value. The OP AMP should be a TL081

What do you think about it?
Regards.
Simon

 

I made an error with the RC.. Should be reversed..

 

That's good thinking, but it's not quite right:
1. TL081 is not appropriate for this application. The outputs typically can only go within 1.5V of the supply rails. This means that with a 5V supply, the output will swing between 1.5V and 3.5V.
2. Op amps in general don't make good comparators, because they are slow when overdriven, i.e., run in open loop mode. In this case, that might not be a problem. However, there are ICs that are designed to be comparators, and they either have logic level outputs or open collector outputs.
3. The capacitor to ground at the noninverting input will defeat the purpuse of the hysteresis, which is to make the output rise and fall times independent of the input rise and fall times.
Assuming that you had a proper comparator, the resistor in series with the PNP emitter needs to be replaced by a wire (no resistor). The PNP is configured as an emitter follower. Emitter followers aren't great in this application, because the emitter voltage will be about 0.7V higher than the base, which will degrade your logic 0 level.
I'm attaching a modified circuit that should do what you want.

 

Thank you for the circuit.

In addition to my scheme, I think about putting a NPN in base common configuration to the OP AMP out to emitter should work..

3. The capacitor to ground at the noninverting input will defeat the purpuse of the hysteresis, which is to make the output rise and fall times independent of the input rise and fall times.

Before posting my last example, I thought about this last: I just was unsure (and I am still unsure right now) about the resisteance, because I saw that normally are putted on the (+) pin comparator.
In simulation seem to be ok..

Regards,
Simon

 

What simulator are you using? Did you use an actual TL081 model, or just a generic op amp?

 

I am using Proteus as simulator, and a EL2004 as OP AMP, but I did not choose it particularly for this purpose. Seems there is not generic Op Amp in Proteus..

It works fine, however respect to the last scheme, it is not needed the 2nd Op Amp, just the first one with the feedback of the NAND to the pin (-). And reversing that RC, putting C to Vcc and R to ground. See scheme.

Regards,
Simon