R/S flip flop usage in DC/DC converters

Thread Starter

myil

Joined May 2, 2020
145
Hi Everyone,
Can anybody explain why R/S flip flop is used in this circuit? I would also like to know how the clock signal should look like in duty cycle?
Last but not least, in R/S flip flop's truth table, it's stated that both set and reset pins shouldn't be turned to high state at the same time. That confuses me if they ever be turned to high in this circuitry. If so, can anybody explain why ?
 

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crutschow

Joined Mar 14, 2008
34,470
In the voltage mode, the clock sets the flip-flop to turn the output driver and transistor ON, and the signal from the comparator comparing the error voltage to the sawtooth voltage (in sync with the clock) turns in off.
This generates the variable duty-cycle (PWM) output needed to control the output voltage.

Make sense?
 

Thread Starter

myil

Joined May 2, 2020
145
I understand that the variable duty cycle is being adjusted in comparator by comparing the sawtooth and Verr. Can't we just use this signal to drive the mosfet? Why do we need a R/S flip flop?
 

Papabravo

Joined Feb 24, 2006
21,228
The periodic clock sets the RS-flip flop at the beginning of each cycle. The RS-flip flop is Reset When the current reaces its maximum value for the design duty cycle or the error amplifier wants to cut the cycle short to reduce the output voltage.
 
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