PWM interlock and dead time question

Thread Starter


Joined Apr 28, 2021
Hi all, am curious about several aspects of this topic. Currently, I have 4 individual PWM signals coming from MCU and into an interlock circuit, I built that goes towards my gate drivers for my h-bridge. The logic is set up in a way that if both signals are high nothing is going to output on top and bottom, my concern is, do I still need dead time in this case? All the dead-time circuits I have seen online seem to give up individual control of 2 signals and just use 1 PWM signal to output 2 separate signals and I don't want to do that as I would like to control my signals individually. I am using an Arduino for prototyping and there seems to be no concrete answer or way to obtain dead time through that.


Joined Oct 7, 2019
The reason for dead time is that without, it is likely that both the top and bottom FETs will be on for a short time. This not good.
We don't have a schematic, probably you need dead time from Top to Bottom FETs and not from Left to Right FETs.