The project in more detail is a frequency counter using mostly all 1970-1980's parts, so no microcontrollers or FPGAs only TTL 7400 logic. I will use nixie tubes to display the output frequency.

For example I have a frequency of

1592874.000Hz that I would like to display on an 8 digit display. I chose 10khz shift, which means the digit just before the dp is worth 100Hz.

Outputting a result of 159.28740. On the display the decimal point moves to correct for the 10 shift and the kHz light is lit.

What I'm currently doing:

Ignoring the counting circuit and output drivers I have one board per digit to control the position of the digits and also contains chips for averaging the result over time(if selected). In this case all it contains is a shift register(74LS194, bidirectional side loading/unloading). Assuming the shift registers have already loaded the counted/averaged frequency.

From the switch on the front panel a range is selected, say kHz, meaning a shift of 3 decimal places must be carried out, I convert the selected number into binary using a DTL diode steering arrangement. The digits are stored as BCD so 4 shifts need to happen to shift the number by one decimal place meaning a total of 12 shifts are needed to put the digits in the correct place.

This is the circuit I came up with to do this:

The counters in the lower left are 74LS162s which is slightly unconventional but it's all I've got at the moment, unless someone knows where I can get some 74LS93s and 74LS90s cheaply(With 70s-80s datecodes) in the UK.

The multiply by 4 is done by shifting the bits 2 bits left.

The XOR/NOT gates compare the current counted number against the desired number of shifts and then the 4inAND will go high when the numbers match and then stop any more clock pulses reaching the clock in of the counter.

The pulse output goes to the clock of the shift registers.

Problem:

You'll notice this is only going to output 4n-1 pulses because as soon as the counter reaches the desired number the clock has already been disabled to the counters clock AND gate.

I can think of two possible ways that I can use to fix this, somehow subtract 1 from the output of the counter probably using an adder using ones complement or some hacky delay that will allow 1 more pulse through before the gate closes.

Or am I completely barking up the wrong tree and theres some simple way of doing this that I've missed?

Thanks in advance for any help.