Problem in cascade of 2 SN74LS192 counters, in real circuit

Thread Starter

roxi60

Joined Sep 2, 2018
48
Hello.
Enclosed you can find my circuit.
Problem is that, when I preset 8 on IC2 and nothing on IC1, I properly have a pulse on pin 13 of IC2 every 80 pulses.
When I preset 8 on IC2 and 2 on IC1 (as enclosed) I have a pulse on pin 13 of IC2 every 2 pulses, as the 80 (or the preset on IC2) would have been lost.

This happens only in real circuit, in Proteus simulation everything's OK.

Thank you in advance for any suggestions.
AA1 02-Sep-18 09.28.gif
 

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MrChips

Joined Oct 2, 2009
19,912
Try putting a 100nF ceramic capacitor and a 10μF electrolytic capacitor across Vcc and GND.

Are IC1 and IC2 74192 or 74LS192?
If it is 74192, change all your input pull-down resistors from 330Ω to 220Ω.

If you are not going to change the divide by 80 function, wire the inputs directly to Vcc or GND as required.
(There are other ways to divide by 80.)
 

Thread Starter

roxi60

Joined Sep 2, 2018
48
Many thanks for your kind actions and replies,Eric and MrChips.
Chips are SN74LS192N of Texas Instruments.
They are in count down configuration.

I will try again your suggestions (I tried to put some capacitors in the past days but with no success).

It is very strange because they singularly work properly, but do not cascade properly: it is as the preset of IC2 is lost in the passage from 13(IC1) to 4 (IC2), when I preset some units in IC1.

The same happens when I preset 40 (run properly) or 41, for examples (run unproperly 1).
Thank you
 

MrChips

Joined Oct 2, 2009
19,912
Do you have any additional 74LS gates handy, such as 74LS00, 74LS04 or 74LS08?
We might try stretching out the CD pulse.
 

MrChips

Joined Oct 2, 2009
19,912
Yes, I have 74S00 and SN7408.
Thank you
Take the quad 2-input AND gate 7408 and chain the four gates so that you get a 4-gate delay.
Do you follow what I mean by this?
Take the CD (BORROW) output from IC2 and feed this into the 4-gate delay.
Take the output of the delay into PL (LOAD) of both IC1 and IC2.
 

Thread Starter

roxi60

Joined Sep 2, 2018
48
Thank you very much.
Unfortunately I do not know how to make a 4 gate delay.
May you kindly sketch the connections?

 

dl324

Joined Mar 30, 2015
9,575
Problem is that, when I preset 8 on IC2 and nothing on IC1, I properly have a pulse on pin 13 of IC2 every 80 pulses.
When I preset 8 on IC2 and 2 on IC1 (as enclosed) I have a pulse on pin 13 of IC2 every 2 pulses, as the 80 (or the preset on IC2) would have been lost.
What frequency is the clock?

Unless you're operating at a frequency that's too high, what you're seeing doesn't make sense.
 

Thread Starter

roxi60

Joined Sep 2, 2018
48
Hello MrChips.
Great suggestions, since most of the couple of IC I tested works properly now !
I say "most", because some of them still have the problem, and mainly when IC2 is preset to pin 9 (most significant digit 8: it is as this pin has to do with load pin, don't know...).

Anyway the few ones that still do not work are not as before, I mean like 62 instead of 2, so not all preset on IC2 is lost.

But again, most of them works nice now.
I tested on a solderless breadboard, and perhaps this does not help...
Actually I still have to clear up my mind to understand theoretically the reason that explains the good working with this delay (does it delay the loading of preset, does it stretch the pulse?)

Dennis, the frequency I run is 100 Hz, but it is not a matter of frequency, as far as I tested.
For your convenience and curiousity enclosed please find my application in a pulse generator circuit.

I have to say many thanks to you again, for your kind assistance and supports!

Regards.
 

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dl324

Joined Mar 30, 2015
9,575
I say "most", because some of them still have the problem, and mainly when IC2 is preset to pin 9 (most significant digit 8: it is as this pin has to do with load pin, don't know...).
That makes no sense. Two clocks on the LSD can't cycle the MSD counter to 0 twice.

Something else is going on...
 
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