If you think 12-bit ADC is impressive, wait till you try a 24-bit ADC.
Mind you, before you become mesmerized with 24 bits, read the ADC datasheet carefully and find out the ENOB (effective by number of bits) which might be 20 bits and which is still very impressive

For comparative purposes, let us compare ADC number of bits with 3V reference,

# bits	# Steps	Resolution μV
8	256	11 719
10	1 024	2 930
12	4 096	732
14	16 384	183
16	65 536	45.78
18	262 144	11.44
20	1 048 576	2.86
22	4 194 304	0.72
24	16 777 216	0.18

 

Obtaining a higher apparent resolution without having the accuracy is an exercise in futility.

agree . . . thats why i said "gonna be a mess but -- in theory possible to deliver what you want "

 

My question is because the generated Sin wave has a flattened, clipped top, yet none of the 12 bit values in the table exceed 0x0FFF. In fact manual inspection of the array shows the expected gradual falling off either side of the 4095, that is the values around element 1024 (90 degrees, a quarter of the way through the array) appear correct yet on the scope the wav has a flat top. Its as if the output reaches some max voltage like 3.3 just before the signal hits 90 degrees, like saturation or something.

Keep in mind that if the DAC is using Vdda as its Vref+ input, your output will not go all the way to the positive rail, nor down all the way to ground. With the DAC buffer turned off, it will come close (within a mV or so), but with the buffer turned on it is not guaranteed to go any higher than Vdda - 0.20 volts, nor any lower then 0.20 volts.

Here's the relevant part of the data sheet, from p. 140:

 

Here's the scope image. The signal is approx 1.3 KHz and the p-p voltage seems to be around 3.3v or so. The width of the flat top seems to be around 75 uS.

75 uS is nearly 10% of the period (769 u S).



this means that the voltage for some 410 of the digital values around element 1024 of the array are either weird or something else is going on.

Now look, here's the array values centered on the peak - 90 degrees, element 1024:



this shows excellent symmtery in the calculated table, the image show 29 points before and after the peak, as you can see they are very reasonable.

As I scroll further down the values look fine, element 1124 = 4070 and element 1224 = 3999, this element approx corresponds to the right hand edge of the flat part of the image.

So it seems the scope is seeing a more or less fixed voltage despite the fact the DAC values are steadily dropping from 4095 to 3999 over the interval (half of the flat part = 37 uS.

Something ain't right!

 

Something ain't right!

Read post #23. I suspect that's the problem.

 

Tweaking the code so that the max generated digital value is 4000 (as opposed to 4095 0x0FFF) "fixes" it - the top of the wave looks perfect.

This means that anything above 4000 (0x0FA0) or less than 95 (0x005F) gets clipped...

That is out of the possible range of 4096 12 bit values some 190-ish are unusable... or about 4.5% of the available range cannot be used (meaning its actually about 11.9 bits !! of a DAC).

I think OBW0549 is spot on.

This is the kind of stuff I enjoy learning !

 

If you think 12-bit ADC is impressive, wait till you try a 24-bit ADC.
Mind you, before you become mesmerized with 24 bits, read the ADC datasheet carefully and find out the ENOB (effective by number of bits) which might be 20 bits and which is still very impressive

For comparative purposes, let us compare ADC number of bits with 3V reference,

# bits | # Steps | Resolution μV
8 | 256 | 11 719
10| 1 024| 2 930
12| 4 096| 732
14| 16 384| 183
16| 65 536| 45.78
18| 262 144| 11.44
20| 1 048 576| 2.86
22| 4 194 304| 0.72
24| 16 777 216| 0.18

+1
https://forum.allaboutcircuits.com/threads/super-moon-shine.100322/post-898360

 

Keep in mind that if the DAC is using Vdda as its Vref+ input, your output will not go all the way to the positive rail, nor down all the way to ground. With the DAC buffer turned off, it will come close (within a mV or so), but with the buffer turned on it is not guaranteed to go any higher than Vdda - 0.20 volts, nor any lower then 0.20 volts.

Here's the relevant part of the data sheet, from p. 140:

View attachment 197326

Thanks OB, I just opened that data sheet and yes I can see these details now. Much appreciated.

Am I right then when I interpret that to mean that in "buffer ON" mode that the lowest voltage will be when the input is 0x0E0 and the highest when its 0xE38 (given a vref of 3.6v).

Any values outside that range will just see the output "saturated" at this min or max voltage?

I can just generate a linear sawtooth actually that will shed more light.

 

Thanks OB, I just opened that data sheet and yes I can see these details now. Much appreciated.

Am I right then when I interpret that to mean that in "buffer ON" mode that the lowest voltage will be when the input is 0x0E0 and the highest when its 0xE38 (given a vref of 3.6v).

Any values outside that range will just see the output "saturated" at this min or max voltage?

Yup. You got it.

(Keep in mind that those voltage levels and DAC codes are only approximate; some units will no doubt do a bit better than that.)

 

Yup. You got it.

(Keep in mind that those voltage levels and DAC codes are only approximate; some units will no doubt do a bit better than that.)

Yes that's a good point, so any real design here would respect those documented levels - this is very interesting - been years since I did anything remotely interesting with electronics.