Powering Digital Logic from a SMPS

Thread Starter

mcardoso

Joined May 19, 2020
116
Getting to the end of my design here...

My circuit (encoder signal interface to servo drive) has a bunch of discrete digital logic gate ICs. I cannot pull power from the servo drive's internal encoder power supply due to the weird way these are wired in the field device (SCARA robot - All the encoders have their power supplies tied together at the robot). Paralleling the encoder power output between all the drives seems like a bad idea since I doubt they are designed for this mode of operation. Also the encoders pull more power than any one drive supply can source (350mA max).

I have 2 options,

1) Provide power to this circuit and the encoders in the field using a low cost industrial 5V SMPS power supply.
https://www.trcelectronics.com/ecomm/pdf/mdr10.pdf
1591801138931.png

2) Power my circuit from the servo drive 5V output for encoder power, and separately power the encoders from the SMPS (tying the DC COM together between the 2 circuits).

Is there concern about directly powering CMOS chips from one of these supplies? A meter on the output gives really nice 5V and you can adjust it in so it is right on the money with load applied.
 

dl324

Joined Mar 30, 2015
10,944
Is there concern about directly powering CMOS chips from one of these supplies?
Commercial switching power supplies will usually be well designed and not leave you with a significant amount of noise on the output. Just make sure you provide adequate supply decoupling. The rule of thumb is one ceramic cap per power pin. You can often get by with less, but sometimes you need more.

A meter on the output gives really nice 5V and you can adjust it in so it is right on the money with load applied.
Measuring DC with a DVM won't tell you much about ripple on the supply because it's changing too fast for the meter to display. For that, you need an oscilloscope.
 

Thread Starter

mcardoso

Joined May 19, 2020
116
Commercial switching power supplies will usually be well designed and not leave you with a significant amount of noise on the output. Just make sure you provide adequate supply decoupling. The rule of thumb is one ceramic cap per power pin. You can often get by with less, but sometimes you need more.
Sounds good. I understand decoupling to be done right at each IC with a 0.1 uF ceramic capacitor immediately adjacent to the Vcc pin of the chip (other side of the cap to GND). Is that correct? How do you know when additional decoupling capacitors will be necessary?

Measuring DC with a DVM won't tell you much about ripple on the supply because it's changing too fast for the meter to display. For that, you need an oscilloscope.
Agreed. Is ripple acceptable as long as it does not exceed the Vin specification for all the chips, or is there a more narrow criteria?

:)Hi there.
No. It looks as though you know what the heck you're talking about and you're more than capable of carrying out that task no problem with the power supply
Thanks, trying to understand all of this. I design big power and control systems for work, but have little experience with PCB level stuff.
 

dl324

Joined Mar 30, 2015
10,944
Is that correct?
Yes, but that's not always sufficient.
How do you know when additional decoupling capacitors will be necessary?
The circuit doesn't work correctly.

When CMOS outputs switch, there's a brief time when both transistors are conducting (the same thing can be said of TTL totem pole outputs). That will put a spike on the power rail. If you get too many outputs switching at the same, or outputs switching at high frequencies, more mitigation may be required. In the case of high switching frequencies (where lead inductance becomes more of a factor), the 0.1uF caps might need to be paralleled with a 0.01uF.

No one really wants to do a detailed analysis of a power grid, but I've seen some application notes for Intel memory products that represented the power grid as a distributed network of R's, L's, and C's to show you how to calculate decoupling requirements.
Is ripple acceptable as long as it does not exceed the Vin specification for all the chips, or is there a more narrow criteria?
There's no rule of thumb. You want it to be low enough, but not chase your tail trying to make it unreasonably low.

I have a Heathkit experimenter that has a bipolar power supply. It's a poor design and has 150mV of ripple at 5V. I used it for years before coming across a circuit that wouldn't work with that much ripple. Can't remember what the circuit was, but I remember that it left me scratching my head because, naturally, power supply ripple was the last thing I checked.
 

dendad

Joined Feb 20, 2016
3,564
Just about all the industrial control stuff I've designed run from switch mode power supplies.
On my circuits, generally, each IC has a 100nF ceramic and there are 10uF Tants around the circuit too.
Probably they have more decoupling then needed, but extra caps are cheap and many of my boards are still in use after 20 years or more.
The parts that have failed are the electrolytic caps. Now days, ceramics are big enough to replace them.
 
Top