I am building a bench power supply that can deliver up to 50 volts at up to 2 amps.

I am seeing an oscillation and can't figure out its source. In the simulation it is a sawtooth at about 40 KHz.
The oscillation varies with load and output voltage.

I have attached LTspice file for a simplified version of my circuit. R2 and D5 are part of a current limit circuit that I removed from the simulation to reduce confusion.


Thanks for any insight on this.

 

It looks to me like your op-amp inputs are labeled backwards.
Anyway...you might limit the bandwidth of the op-amp with a capacitor or series RC from the output to the inverting input, or increase its ripple feedback with a capacitor across R9.

 

It looks to me like your op-amp inputs are labeled backwards.

No, it's correct. Transistor M4 adds an inversion.

Anyway...you might limit the bandwidth of the op-amp with a capacitor or series RC from the output to the inverting input, or increase its ripple feedback with a capacitor across R9.

I don't think it is a bandwidth or compensation problem since the oscillation is not sinusoidal. Also, amplifier compensation does kill the "normal" sinusoidal oscillation but not the sawtooth oscillation.

By ripple do you mean power supply filter ripple? There is no power supply ripple in the simulation.

I could be wrong here, however. If I understood it I would have fixed it.

 

Your capacitors are being charged and discharged at the 40 kHz rate. Why do you have 4.7KΩ in parallel with your 22.2KΩ voltage divider. Look at the opamp output signal and see that you might benefit from some hysteresis or less sensitivity around the threshold.

 

Your capacitors are being charged and discharged at the 40 kHz rate. Why do you have 4.7KΩ in parallel with your 22.2KΩ voltage divider. Look at the opamp output signal and see that you might benefit from some hysteresis or less sensitivity around the threshold.

The 4.7 K is there to discharge the output caps in a couple of seconds with a light external load. That way I am less likely to be working on a live circuit just after turning the power supply off.

This is supposed to be a linear voltage regulator. Wouldn't adding hysteresis make it more likely to oscillate?

 

Your capacitors are being charged and discharged at the 40 kHz rate. Why do you have 4.7KΩ in parallel with your 22.2KΩ voltage divider. Look at the opamp output signal and see that you might benefit from some hysteresis or less sensitivity around the threshold.

I put a single pole RC filter of 27.4K and 1 μF between the output of the opamp and the gate of M4 Cleaned things right up.

 

I put a single pole RC filter of 27.4K and 1 μF between the output of the opamp and the gate of M4 Cleaned things right up.

Okay. I tried it and your fix works. But why???

 

I put a single pole RC filter of 27.4K and 1 μF between the output of the opamp and the gate of M4 Cleaned things right up.

Oops. Not completely fixed. I increased the stop time to 20ms and I now see a sinusoidal oscillation at about 2.5 KHz.

 

The output capacitors are charging and discharging by very small amounts. A little bit of charge above the threshold and you cutoff the voltage supply. The output capacitor discharges a little bit and you turn it back on. So it is ON/OFF at 40 kHz. With the filter in place you slow down the response of the control loop so that it tracks long term changes. The tradeoff for this is that transient response to load changes will be more measured. Expand the time scale and look at what happens when you apply a load transient.

 

Is there some reason why you are using an OpAmp in the open loop configuration? That right there explains a good deal of the sensitivity around the reference point.

 

No, it's correct. Transistor M4 adds an inversion.

Aaack! I read that as 2 inversions. My bad.

By ripple do you mean power supply filter ripple? There is no power supply ripple in the simulation.

No, I meant the ripple on the output...again working from the wrong belief that you had 2 inversions.

crutschow slowed down the first gate signal, which is the same thing as limiting the bandwidth of the op-amp. He's making a sort of integrator in the drive side. I was talking about feeding the bad stuff back to the op-amp inverting input with a capacitor so the op-amp would anti-ripple at whatever frequency the output is rippling, including having a fast response to load transients. I would invert the op-amp and use a P-channel for M5 so I could use the inverting input for a ripple filter by placing a capacitor across R9. That would pass the ripple voltage and load transients to the inverting input without their voltage being reduced by the R9-R10 voltage divider.

I expect to be locked out of this Thread rather quickly by my refusal to install LTspice (and my complete ignorance about how to use it).
Doesn't matter. crutschow is better than I at this sort of thing.

 

I'm signing off for now but I have some things to think about...

 

Aaack! I read that as 2 inversions. My bad.

No, I meant the ripple on the output...again working from the wrong belief that you had 2 inversions.

crutschow slowed down the first gate signal, which is the same thing as limiting the bandwidth of the op-amp. He's making a sort of integrator in the drive side. I was talking about feeding the bad stuff back to the op-amp inverting input with a capacitor so the op-amp would anti-ripple at whatever frequency the output is rippling, including having a fast response to load transients. I would invert the op-amp and use a P-channel for M5 so I could use the inverting input for a ripple filter by placing a capacitor across R9. That would pass the ripple voltage and load transients to the inverting input without their voltage being reduced by the R9-R10 voltage divider.

I expect to be locked out of this Thread rather quickly by my refusal to install LTspice (and my complete ignorance about how to use it).
Doesn't matter. crutschow is better than I at this sort of thing.

I don't see where @crutschow has even contributed to this thread {EDIT: up to this point in the thread}. I know he is good, but even he would not take credit for a contribution he did not make.

 

crutschow slowed down the first gate signal

Wasn't me.
You referring to PB's post?
Too much nog today?

As shown below, I added C2 and R5, to control the loop gain, which seems to cure the problem (at least in simulation).
Putting them there also solves the overshoot problem I noticed on startup when placing compensation at the op amp output.
Note that C2 by itself is not sufficient. You also need R5 for proper compensation.
The values shown for C2 and R5 seem to give the least peaking in the Bode plot of the loop response (not shown).
I simulated at several different output voltages by stepping the value of R9 to determine that it was stable for various output voltages.

 

Elegant -- to say the very least!

 

I don't see where @crutschow has even contributed to this thread. I know he is good, but even he would not take credit for a contribution he did not make.

Geeze! My eyes must be playing tricks on me. Maybe I should go work on a truck for a few days.

This is as bad as the time I told somebody, "Welcome to Electro-tech-online"

 

Posted too soon.
It's unstable with no load.
Working.....

 

Geeze! My eyes must be playing tricks on me. Maybe I should go work on a truck for a few days.

This is as bad as the time I told somebody, "Welcome to Electro-tech-online"

I think you just might have built up enough credits to get a pass on this one.
LTSpice lessons, one flight up
Open all night

 

Okay here's my further revised circuit which simulates as stable for both the 10 ohm load and no load.
Changing C2 to 20μF seems to do the trick.

 

Okay here's my further revised circuit which simulates as stable for both the 10 ohm load and no load.
Changing C2 to 20μF seems to do the trick.View attachment 116901

Thanks.
I will play with it and see if I can break it.

I am wondering if you have an idea why the original circuit had the sawtooth oscillation.

Looking back, I am thinking that the culprits might be the huge input capacitance of M3 in combination with the high value of R1 as well as the high output capacitance load. I suspect that either removing the 47 uF cap or at least putting a small resistor in series with it might help.

Along similar lines, do you think that using a faster op-amp would allow smaller values for your compensation network?