Hi guys,

For this project, I had to want to reduce the power dissipation (< 2 mW) when the Rload is 54 Ω. These are the two circuits that I have employed.



When I sweep the pwm frequency vs Pdiss (power dissipation of the buck converter), without/with the gate driver, I have the following:




From those two plots with out gate drivers, I see that including gate drivers I increase the power dissipation by increasing switching frequency, but when excluding gate drivers, the power dissipation will decrease with increasing switching frequency. Hence, why is that?


Furthermore, is there a solution to solve this? Maybe decreasing the gate driver area?


The output voltage of the synchronous buck converter is 1.2 V and all other parameters are the same in both the circuits.

 

1v2 out, whats the input voltage ?
1v2 at what 20 mA output ?
have you seen these
https://www.digikey.co.uk/en/produc...++E+OJAAFoetBIVAvgBXOEkslIW5AkElBEAExQkpRQKAA

 

1v2 out, whats the input voltage ?
1v2 at what 20 mA output ?
have you seen these
https://www.digikey.co.uk/en/products/detail/torex-semiconductor-ltd/XCL210D121GR-G/5964731?s=N4IgjCBcpmBMAGKoDGUBmBDANgZwKYA0IA9lANrgBsArDQMxwjFhX0AcA7J8+OwCwIq7XmHZU47Gr35VuATn6j2AxaPkJ6-Hi3bzW04rJpsd4feKVGa8zvKbE4YbXt5Oq2qjNpUqSR2A0nHBmTpx6Xo5wiAxuHGAIEI6CnAih-JIIIka0NvLeNuz+IHD8-LahQYzFcDZ0kSV+QdmNrPT5jhL69G5sUlYg-DZ2PZ30jEmNQ+W9DO29VGD2BX41nBylbtysDiXhdgOSwfINR-RgoyV6Nj0AusQADgAuUCAAyk8ATgCWAHYA5iAAL4sGi1ZAgNCQLB4IikCiDLiJED3EDPV4fH4A4FRWAQqEwgjEMiQSgQVHoyAgACSvye+H++E+OJAAFoetBIVAvgBXOEkslIW5AkElBEAExQkpRQKAA

Thank you for your answer.
the input voltage is 3.6 V from a battery for example.
The output current is 20 mA.

The link that you have shared with me is a pcb component. However, the goal is to design this circuit on a integrated circuit level in 180 nm technology using cadence rather than taking the DC-DC converter PCB component.

 

Thank you for your answer.
the input voltage is 3.6 V from a battery for example.
The output current is 20 mA.

The link that you have shared with me is a pcb component. However, the goal is to design this circuit on a integrated circuit level in 180 nm technology using cadence rather than taking the DC-DC converter PCB component.

OK, sorry it was not obvious you were looking for an ASIC level design,

a simple LDO would drop what power ?