Hi everyone,

I am studying the PN junction and I have learnt that in open circuit condition it has a built-in voltage (here called B) determined by the difference in fermi level of its n-doped and p-doped parts.
Then we can apply, for example, a forward bias, this will lower the voltage barrier, and therefore electrons can start flowing from n to p side, establishing a current.
If the forward bias is Va then we say in such condition the voltage across the depletion layer in the junction is B-Va.
The remaining part of the junction is said to be a neutral region with no voltage drop on it.
My question is: since we are applying Va with a voltage generator across the PN junction, but the voltage drop across the depletion layer is B-Va, and there is no voltage drop in any other point of the circuit, it seems to me that the second Kirchhoff's law is violated, as if I sum the voltage drops around this loop I won't get zero.
Far from me thinking that either the PN junction theory or Kirchhoff's law are wrong, what is the mistake I am doing in my considerations?

Thank you very much for any help in fixing this hole in my understanding

 

Hi everyone,

I am studying the PN junction and I have learnt that in open circuit condition it has a built-in voltage (here called B) determined by the difference in fermi level of its n-doped and p-doped parts.
Then we can apply, for example, a forward bias, this will lower the voltage barrier, and therefore electrons can start flowing from n to p side, establishing a current.
If the forward bias is Va then we say in such condition the voltage across the depletion layer in the junction is B-Va.
The remaining part of the junction is said to be a neutral region with no voltage drop on it.
My question is: since we are applying Va with a voltage generator across the PN junction, but the voltage drop across the depletion layer is B-Va, and there is no voltage drop in any other point of the circuit, it seems to me that the second Kirchhoff's law is violated, as if I sum the voltage drops around this loop I won't get zero.
Far from me thinking that either the PN junction theory or Kirchhoff's law are wrong, what is the mistake I am doing in my considerations?

Thank you very much for any help in fixing this hole in my understanding

For starters you would never apply an ideal voltage source to a pn-junction. Neither the transistor itself, nor the pn-junction is a voltage device. It is a current device. When properly biased with a voltage divider, for example, there is an approximately 0.7v drop across the BE junction and a corresponding voltage rise across the lower leg of the voltage divider. The sum of the voltage drops and rises around that loop is identically zero.

Also the currents in the upper leg of the voltage divider, the lower leg of the voltage divider, and the base current will sum to 0.

 

I am not entirely sure if this is a good way of explaining it but it has helped me easily solve diode circuits. I view the PN junction as a sort of wall or barrier that carriers can pass through but need a push to have the force needed to pass through the barrier and recombine. This force is the voltage and once the force is big enough to move the carriers across, we see conduction with that voltage dropped across the junction. Again I am not sure how accurate this description actually is but it has never let me down in circuit analysis.

 

For starters you would never apply an ideal voltage source to a pn-junction. Neither the transistor itself, nor the pn-junction is a voltage device. It is a current device. When properly biased with a voltage divider, for example, there is an approximately 0.7v drop across the BE junction and a corresponding voltage rise across the lower leg of the voltage divider. The sum of the voltage drops and rises around that loop is identically zero.

Also the currents in the upper leg of the voltage divider, the lower leg of the voltage divider, and the base current will sum to 0.

Thank you for your answer. So supposing we are in the scenario depicted by you, with such voltage divider, with a 0.7V drop across BE junction. Doesn't this mean that if we look at the band diagram of such junction, the conduction band of the p-doped part (base) will be 0.7eV lower than in open circuit condition? But then according to my microelectronics course this would mean that the voltage drop across the depletion region of such BE junction would be B-0.7V, and not 0.7V (again B is built in potential) right? (That is at least the voltage we use to calculate the depletion region width, stored charge in the junction as well as other parameters).
Basically whether it is an ideal voltage source or not, I still don't understand the discrepancy in what is the voltage across the junction calculated from a circuit perspective and the one which is said to be across the depletion region of the junction (because from the device perspective this would be the built in potential lowered by the forward bias voltage). Isn't it still the same situation which I depicted previously?

 

I am not entirely sure if this is a good way of explaining it but it has helped me easily solve diode circuits. I view the PN junction as a sort of wall or barrier that carriers can pass through but need a push to have the force needed to pass through the barrier and recombine. This force is the voltage and once the force is big enough to move the carriers across, we see conduction with that voltage dropped across the junction. Again I am not sure how accurate this description actually is but it has never let me down in circuit analysis.

Thanks for your answer! I understand the fact that applying the bias voltage can lower/raise the barrier for the carriers (looking at the band diagram for example), but still I don't figure out how this voltage bias isn't the same which is across the depletion region of the device, is this last one to be considered like a sort of "fictitious" voltage?

 

Thank you for your answer. So supposing we are in the scenario depicted by you, with such voltage divider, with a 0.7V drop across BE junction. Doesn't this mean that if we look at the band diagram of such junction, the conduction band of the p-doped part (base) will be 0.7eV lower than in open circuit condition? But then according to my microelectronics course this would mean that the voltage drop across the depletion region of such BE junction would be B-0.7V, and not 0.7V (again B is built in potential) right? (That is at least the voltage we use to calculate the depletion region width, stored charge in the junction as well as other parameters).
Basically whether it is an ideal voltage source or not, I still don't understand the discrepancy in what is the voltage across the junction calculated from a circuit perspective and the one which is said to be across the depletion region of the junction (because from the device perspective this would be the built in potential lowered by the forward bias voltage). Isn't it still the same situation which I depicted previously?

I do not think that is correct. The forward bias on the base terminal reduces the height of the potential barrier so that current carriers with much lower energies can go over the potential wall and down the other side. When one type of carrier moves in one direction the opposite carrier moves in the other direction. In the equivalent circuit for a transistor you don't actually see an elelment in the the base emitter circuit that looks like a voltage source. What you do see is a current source in the collector emitter circuit whose current is proportional to the base current.

check out page 3 of the following:
https://coefs.uncc.edu/dlsharer/files/2012/04/C3.pdf

 

But then according to my microelectronics course this would mean that the voltage drop across the depletion region of such BE junction would be B-0.7V, and not 0.7V (again B is built in potential) right? (That is at least the voltage we use to calculate the depletion region width, stored charge in the junction as well as other parameters).

I believe what your claiming is that because there’s a voltage potential barrier at the PN junction there should be no voltage drop? Is this correct since you say it should be VB - Vf not just Vf...

here are some notes

1. it’s not a voltage source, it’s a difference in potential think about this.

2. a good way to model this is as a one way battery. A 0.7V battery that only allows conduction when the circuit source can reverse the 0.7v. You will see a 0.7V drop in such as circuit. A model could be built using a PMOS with gate to ground.

In the model above the total voltage is VCC-0.7 of the battery. Hope this is clear

 

I do not think that is correct. The forward bias on the base terminal reduces the height of the potential barrier so that current carriers with much lower energies can go over the potential wall and down the other side. When one type of carrier moves in one direction the opposite carrier moves in the other direction. In the equivalent circuit for a transistor you don't actually see an elelment in the the base emitter circuit that looks like a voltage source. What you do see is a current source in the collector emitter circuit whose current is proportional to the base current.

check out page 3 of the following:
https://coefs.uncc.edu/dlsharer/files/2012/04/C3.pdf

As you say indeed in the equivalent circuit I don't see such voltage source, but still in every calculation that we perform by studying the device such built in potential is taken into account and is generated by the depletion region... now I am not sure whether that voltage source is not seen just because the built in potential is constant and therefore in the small signal model it becomes a short circuit, or for other reasons, but I cannot see why we would have such a potential across the depletion region (given by the difference between the fermi levels of the two sides of the PN junction), which is different by the voltage we apply from external

 

I believe what your claiming is that because there’s a voltage potential barrier at the PN junction there should be no voltage drop? Is this correct since you say it should be VB - Vf not just Vf...

here are some notes

1. it’s not a voltage source, it’s a difference in potential think about this.

2. a good way to model this is as a one way battery. A 0.7V battery that only allows conduction when the circuit source can reverse the 0.7v. You will see a 0.7V drop in such as circuit. A model could be built using a PMOS with gate to ground.

In the model above the total voltage is VCC-0.7 of the battery. Hope this is clear

Thank you for your answer,
1. I searched a bit the internet, couldn't really find a clear difference between voltage source and difference in potential, what are you referring to there?
2. I am not sure to understand your example. The fact is everytime we look at circuits, such built in potential is never taken into account, nevertheless it is there in the physical model of the device

 

As you say indeed in the equivalent circuit I don't see such voltage source, but still in every calculation that we perform by studying the device such built in potential is taken into account and is generated by the depletion region... now I am not sure whether that voltage source is not seen just because the built in potential is constant and therefore in the small signal model it becomes a short circuit, or for other reasons, but I cannot see why we would have such a potential across the depletion region (given by the difference between the fermi levels of the two sides of the PN junction), which is different by the voltage we apply from external

The potential is not constant, it is in fact exponential. Past a certain threshold it appears "almost" linear. It is not -- trust me on this. Since it is exponential, the slope is proportional to the value at any given point, so it is constantly changing. Below the threshold the currents are very small. This whole bit of behavior is nonlinear. We can however linearize this behavior around an operating point and that is in fact what is going on.

 

Thank you for your answer,
1. I searched a bit the internet, couldn't really find a clear difference between voltage source and difference in potential, what are you referring to there?
2. I am not sure to understand your example. The fact is everytime we look at circuits, such built in potential is never taken into account, nevertheless it is there in the physical model of the device

A voltage source will attempt to maintain the output, by supplying the required current, at it's open circuit value as long as the internal resistance is small with respect to the load. A voltage drop is modeled as a passive resistor and has no ability to maintain any value. It is only a function of the current going through it. An ideal voltage source will have zero internal resistance.

 

The potential is not constant, it is in fact exponential. Past a certain threshold it appears "almost" linear. It is not -- trust me on this. Since it is exponential, the slope is proportional to the value at any given point, so it is constantly changing. Below the threshold the currents are very small. This whole bit of behavior is nonlinear. We can however linearize this behavior around an operating point and that is in fact what is going on.

Yes, I must have explained myself unclearly, what I meant is that the potential difference across the depletion region of a PN junction is made of two components, its built-in potential, minus the forward bias applied. The forward bias applied is what determines (according to my understanding) the concentration of minority carriers in the two sides of the junction, therefore determining the exponential behavior of the junction's current versus the forward bias.

Maybe I can be more clear with the aid of the picture below, where a PN junction is represented in forward bias conditions versus no bias applied
The built-in component of the voltage drop across the depletion region is ϕ0= ϕn - ϕp , while the component due to the external bias is -V, indeed we say the potential drop across the junction is ϕ0-V, according also with the picture.
But then here I don't understand why it wouldn't be legitimate here to apply Kirchhoff's law and say that doing the loop of the circuit (ϕ0-V)+V (depletion region in series with the voltage source) we shouldn't get a sum of zero.

I know that looking at the models used for circuits calculations (like the ones you linked here before for example) such ϕ0 never comes into play (otherwise Kirchhoff law indeed would seem to fail) but then why do we say it is there such a built-in potential? what is it actually? is it really a voltage drop?

Thank you again for your help

 

Yes, I must have explained myself unclearly, what I meant is that the potential difference across the depletion region of a PN junction is made of two components, its built-in potential, minus the forward bias applied. The forward bias applied is what determines (according to my understanding) the concentration of minority carriers in the two sides of the junction, therefore determining the exponential behavior of the junction's current versus the forward bias.

Maybe I can be more clear with the aid of the picture below, where a PN junction is represented in forward bias conditions versus no bias applied
The built-in component of the voltage drop across the depletion region is ϕ0= ϕn - ϕp , while the component due to the external bias is -V, indeed we say the potential drop across the junction is ϕ0-V, according also with the picture.
But then here I don't understand why it wouldn't be legitimate here to apply Kirchhoff's law and say that doing the loop of the circuit (ϕ0-V)+V (depletion region in series with the voltage source) we shouldn't get a sum of zero.

I know that looking at the models used for circuits calculations (like the ones you linked here before for example) such ϕ0 never comes into play (otherwise Kirchhoff law indeed would seem to fail) but then why do we say it is there such a built-in potential? what is it actually? is it really a voltage drop?

Thank you again for your help

View attachment 226101

I guess you have had such badass supervisor for electronics course as me, that's pushed you into bare calculations without any philosophy and open vision about electronics.
as you can see in ϕ-x diagram, the pn junctions accurately works like an ideal linear resistor in range of -Xp to Xn (small signal) that usually called Rπ in small-signal transistor model.
but beyond this range (large signal) ,it works like a constant voltage or voltage source (that is ineed a sharp exponential trend).
so, you simply should devide your Kirchhoff or other calculations into "Superposition" of "small signal" and "large signal".
for using transistor in small signal , you usually us an AC bias with small values(-Xp - Xn) to use benefit of linearity of transistor junction.
and for large signal, you can assume an applied DC bias voltage that pushes the junction in a constant voltage source (Vbe=0.7v).
finally superposing these two analysis with convenience of mind then.

 

Hi everyone,

I am studying the PN junction and I have learnt that in open circuit condition it has a built-in voltage (here called B) determined by the difference in fermi level of its n-doped and p-doped parts.
Then we can apply, for example, a forward bias, this will lower the voltage barrier, and therefore electrons can start flowing from n to p side, establishing a current.
If the forward bias is Va then we say in such condition the voltage across the depletion layer in the junction is B-Va.
The remaining part of the junction is said to be a neutral region with no voltage drop on it.
My question is: since we are applying Va with a voltage generator across the PN junction, but the voltage drop across the depletion layer is B-Va, and there is no voltage drop in any other point of the circuit, it seems to me that the second Kirchhoff's law is violated, as if I sum the voltage drops around this loop I won't get zero.
Far from me thinking that either the PN junction theory or Kirchhoff's law are wrong, what is the mistake I am doing in my considerations?

Thank you very much for any help in fixing this hole in my understanding

Title: Understanding Basic Electronics, 1st Ed.
Publisher: The American Radio Relay League
ISBN: 0-87259-398-3

 

Here's the thing: that internal voltage you are having trouble with is just that: an internal voltage. It counterbalances the force of diffusion which tries to move electrons from the N to the P (and holes from the P to the N). Think of it as a "hidden" voltage. When you apply an external bias, in the forward direction, this reduces the internal potential and allows the diffusion to flow with less opposition. In the reverse direction it generates a larger electric field with a wider depletion region and reduces the diffusion current even lower than it already was. With no bias at all there is no measureable voltage across a diode - apart from noise caused by random motion of a few electrons and holes moving back and forth. If that internal potential were present on the terminals we'd all have free electricity!
At very low voltages (a few mV) either way, the diode looks more like a capacitor. For silicon it is only when the voltage gets to be about 0.6V that high currents flow. In fact, that is what tells us the internal voltage is about 0.6V.
If you apply 300mV across a diode, that is what you measure. Internally, the hidden voltage will have reduced from 0.6V (let's say) to 0.3V, but that is only determined from the current flowing. The exact voltage depends on the diode construction.