Power dissipated on a die at the junction between FEOL and BEOL

Thread Starter


Joined Nov 3, 2023

I have a logic die that has a junction between two silicon+FEOL and BEOL layers. In the silicon+FEOL layer, I have two TSVS (TSV1 and TSV2) which terminate right at the junction. There are no other connectors. I also have the total dissipated power in the junction (25W).

1) At the areas of the junction close to TSV1 and TSV2 (A, C), is the power dissipated greater or less than other areas (B, for example) ?

2) Is there a way to calculate an approx value of the dissipated power at A and C, based on the above total dissipated power ? I can also provide TSV's areas and thickness, their thermal conductivity, as well as the SILICON + FEL and BEOL stratas' thermal conductivity, thickness, width and height and thickness.