Phase shifted clock generator

Thread Starter

knight04

Joined Apr 2, 2020
3
Hello everyone !
For my PhD project I need to design a high frequency single phased inverter with 60 degrees phase shift between legs control signals (in order to cancel the 3rd harmonic at the output).
I found the LTC6909 (datasheet here) which can give 6 outputs phase shifted by 60°. However the frequency with this device is set using an external resistor. Hence I'm looking for a programmable (I2C or whatever) clock/oscillator and preferably with a lower jitter than LTC6909 and a higher frequency resolution (5 kHz resolution at around 2 MHz would be enough).
So I was wondering if anyone could help me to find such a device please.

Thanks in advance
 

RPLaJeunesse

Joined Jul 29, 2018
92
Generating 6 outputs phase shifted by 60° can be done many ways: 1. Shift register with gating to produce 50% duty input. 2. A CPLD or FPGA that does the same as #1. 3. a fast microcontroller designed for 3-phase motor control. For frequency control there are many DDS chips out there that would allow high=resolution frequency adjustment.
 

danadak

Joined Mar 10, 2018
4,057
Can you supply a timing diagram of goal. Do you want outputs to be 50%, overlapping,
or a duty cycle of 1/6, no overlap with or without dead band ?

A simple 3 bit counter set up as /6 driving a demux, would that do ?


Regards, Dana.
 

Thread Starter

knight04

Joined Apr 2, 2020
3
Generating 6 outputs phase shifted by 60° can be done many ways: 1. Shift register with gating to produce 50% duty input. 2. A CPLD or FPGA that does the same as #1. 3. a fast microcontroller designed for 3-phase motor control. For frequency control there are many DDS chips out there that would allow high=resolution frequency adjustment.
Thank you very much for your reply and sorry to be bit late.

- For the 2 first solution, I unfortunately don't have solid base in electronics (that's a shame I know) I barely know how shift registers work. I'll try to search and see how the phase shifting needs to be done. Meanwhile if already you have any document/reference on the topic I would be interested in.

- I'd also though using an FPGA with a high frequency input clock to generate control signals digitally. But for my required resolution of 5 kHz at 2 MHz switching frequency I would need a master clock of about 700 MHz. I already tried the internal clock of an old Altera DE2 multiplied using a PLL to 350 MHz but it was not precise enough. And I though it was easier and more reliable to generate the signal using an external IC/circuit shifting the phases (please correct me if I'm wrong).

- I've relatively searched a lot for a 3-phase motor control component but unfortunately couldn't find any device fast enough (until now).

Thanks a lot again :)
 

Thread Starter

knight04

Joined Apr 2, 2020
3
Can you supply a timing diagram of goal. Do you want outputs to be 50%, overlapping,
or a duty cycle of 1/6, no overlap with or without dead band ?
Thank you very much for Dana for you reply.

The diagram is simple. I have an H-bridge with 4 MOSFET switches.
2 complementary control signals are fed to the switches 1 & 2 (high side and low side switches respectively) of the first leg. Signals are full wave, 50% duty cycle and overlapping. The overlap protection and the dead band are then controlled using the opto-driver IC (Si8234).
The signals of the first leg are then shifted by 60° and fed to switches 4 & 3 of the second leg (Or shifted by 120° and fed to switched 3 & 4).

A simple 3 bit counter set up as /6 driving a demux, would that do ?
Unfortunately I don't have solid base in electronics. I'll try to search and do some simulations and tell if it can works.

Thank you very much again

ps : If you already have a solution for generating the dead band using electronic components I would also be interested in.
 

danadak

Joined Mar 10, 2018
4,057
Here is a phase shifted solution - https://forum.allaboutcircuits.com/threads/555-timer-phase-shift.168664/#post-1498121
That thread gens the 60 degree 50% duty cycle 3 phase clock.

1586603054169.png



The same part has PWMs with dead band control in them -

1586605221324.png



Here is config wizard for PWMs showing setup to do the deadband -

1586604401420.png

This is single chip, still plenty of other resources left, see right hand window, resources used/left.


This chip is PSOC. I perceive the problem here is your level of experience to use a tool like this. If you are
inexperienced in IDE processor development this might be too heavy a lift for you as a first time experience.
The easy part is drag and drop and wire up. The challenge is coding. The above example would be code
for changing PWM. Its not rocket science code, but being C its not trivial either. Just some thoughts. If
you hooked up with a PSOC experienced designer its straightforward.



Regards, Dana.
 

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danadak

Joined Mar 10, 2018
4,057
I just realized my clock is only 3 phases, you need 6 phases. This should work, still one chip -

1586612383743.png

LUT_2 is a /12 counter, LUT_1 does the phase decode.

What is controlling the PWM duty cycle ? Is it a V or I being measured ? There is also A/D onboard
that can be used for that.

What is clock rate and resolution you need in PWM's ? Note if you need fine res of clock freq could have used the DDS onchip
component as input to the LUT counter. All depends on some of your answers to above.


Regards, Dana.
 
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RPLaJeunesse

Joined Jul 29, 2018
92
Dana, while your PSOC design will generate 6 phases it cannot do what the OP requested. That request was for 6 phases at 2MHz, with tuning to 5KHz resolution. In my view the OP's request was not exactly clear as to what was truly required. I suspect it might be the need is for 3 each of identically duty cycled 2MHz (or so) PWM signals, each shifted by 120 degrees, plus complements with some degree of non-overlap. Just getting 8-bit PWM at 2MHz requires a 512MHz clock, not for the faint of heart. At 60Hz almost any small micro could do this, but 2MHz is a killer. Add in tuning, and the 512MHz needs to be derived from a variable frequncy source, likely PLL locked to a proper 1.28MHz (or less) reference.
 

danadak

Joined Mar 10, 2018
4,057
Dana, while your PSOC design will generate 6 phases it cannot do what the OP requested. That request was for 6 phases at 2MHz, with tuning to 5KHz resolution. In my view the OP's request was not exactly clear as to what was truly required. I suspect it might be the need is for 3 each of identically duty cycled 2MHz (or so) PWM signals, each shifted by 120 degrees, plus complements with some degree of non-overlap. Just getting 8-bit PWM at 2MHz requires a 512MHz clock, not for the faint of heart. At 60Hz almost any small micro could do this, but 2MHz is a killer. Add in tuning, and the 512MHz needs to be derived from a variable frequncy source, likely PLL locked to a proper 1.28MHz (or less) reference.
I concur partially, I am making too many assumptions.

I was thinking the 6 phase clock out was at 2 Mhz,, so its source would have to be 24 Mhz,, that the PWMs were sourced from the 2 Mhz. phases, and that
the 5 Khz was off the PWM period which is a subset of the 2 Mhz.

The LTC osc chip he is taking about only good for 6+ Mhz. So does not make sense with rest of specs.....?

Getting ahead of myself until TS comes back with more info.


Regards, Dana.
 
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