Hello,

For a university project I am currently designing a radio frequency oscillator which will generate a carrier wave with a frequency of approximately 100MHz. A variable capacitance diode will then be used to apply frequency modulation to the carrier wave, using an audio signal with an amplitude of approximately 140mV and a frequency of 20Hz-20kHz that is supplied to the variable capacitance in order to modulate the audio signal onto the carrier wave.

I am aware that parasitic inductances of the used wires have to be taken into account when desiging a circuit for such a high frequency, and as a rule of thumb I assume that a wire has an inductance of 1nH per mm of wire length. The circuit including the parasitic inductances is modelled in LTSpice, see the attachment for the circuit schematic.

The issue is that very large cables are used to connect the circuit to the power supply, thus leading to a large parasitic inductance between the power supply and the rest of the circuit. Also, there are a few points in the circuit where these parasitic inductances can cause problems. I have heard it is possible to get rid of the imaginary impedance of an inductor (jωL) by placing a capacitor (1/jωC) in parallel with it, which then cancels out the complex impedance of the inductor. However, how exactly is this done and how does one calculate the required value of the capacitor that is placed in parallel with a certain parasitic inductance? E.g. if I was to place a capacitor in parallel with the 10uH inductance from supply to R1 and R2, what value should this capacitor have in order to get rid of the complex impedance of the inductor?

Thanks in advance!

Circuit schematic using LTSpice:


PS: sorry for the orange background

 

[QUOTE="Henkdesteen, post: 1258652, member: 511045"I am aware that parasitic inductances of the used wires have to be taken into account when desiging a circuit for such a high frequency, and as a rule of thumb I assume that a wire has an inductance of 1nH per mm of wire length. The circuit including the parasitic inductances is modelled in LTSpice, see the attachment for the circuit schematic.

The issue is that very large cables are used to connect the circuit to the power supply, thus leading to a large parasitic inductance between the power supply and the rest of the circuit. Also, there are a few points in the circuit where these parasitic inductances can cause problems.

Circuit schematic using LTSpice:
View attachment 150270[/QUOTE]
There are also parasitic capacitances in the circuit. You need to model them as well.

The way to get rid of the inductance of the power supply wiring is to use power supply bypass capacitors. These are capacitors between the power supply voltage and ground. These caps must be close to the circuit so that the power supply inductance is between the power supply and the circuit.

There is a discussion on the forum about this. Hopefully someone will have the link to it.