Hi,

When using linear regulators, I have always been told that to ensure the output is stable, to use a resistor of about 1Ohm in series with the output if using MLCC type capacitors, either X7R or C0G, since their own output ESR is so low.

In more modern day LDO data sheets I never see anything like this, and also there is no description about a minimum ESR for the supply to be clean and stable. What does everyone else here do when designing an LDO? is it prudent to have a DNP component in series with the C0G/X7R capacitors, such that a 1R resistor can be soldered in if it is found the supply is not stable.

Additionally: why does this ESR limit only exist on the output of an LDO? Why is there no such requirement for a certain level of ESR for stability on the regulator input capacitors?

Regards,
SIC

 

Hi,

When using linear regulators, I have always been told that to ensure the output is stable, to use a resistor of about 1Ohm in series with the output if using MLCC type capacitors, either X7R or C0G, since their own output ESR is so low.

In more modern day LDO data sheets I never see anything like this, and also there is no description about a minimum ESR for the supply to be clean and stable. What does everyone else here do when designing an LDO? is it prudent to have a DNP component in series with the C0G/X7R capacitors, such that a 1R resistor can be soldered in if it is found the supply is not stable.

Additionally: why does this ESR limit only exist on the output of an LDO? Why is there no such requirement for a certain level of ESR for stability on the regulator input capacitors?

Regards,
SIC

Its an old saying ,

The reason, is how a LDO works,
At the basics, its a negative feedback amplifier,

So if the current and voltage are out of phase on the output ,
the amplifier in the feedback can oscillate.

In days of old,
we used electrolytic capacitors, or even paper capacitors as the big boys, and smaller capacitance ceramics.
These big boys, have a high ESR ( Efective Series Resistance )

so LDO were designed for that sort of output impedance, and had a minimum of about 1.5 drop across them

But 20 years ago, when Tants and then Ceramics became normal,
and the ESR started to fall, the old LDO's had problems, and "recommended" a long track / series resistance...

But IMHO "all" LDO of last 20 years , have a new topology, and very low minimum voltage drop,
and normaly the data sheet says "ceramic safe" or word s to that effect,
Its so common now, that some just have ceramics in the example circuit they all show,

EDIT:
just found this , could not find it for looking !!

https://www.ti.com/lit/pdf/snva167#...tors extremely,for the loop compensation zero.