That's not what crutschow is saying. The resistor is not connected to ground, meaning the low end is not at ground potential. But something else is connected between that end and ground, further restricting current. So you have in effect, a voltage divider. The voltage at the low end of the resistor is between V+ and ground. Please google "voltage divider" for more information.

I think I already understand the concept of voltage dividers. But, I'm not sure how one would do the calculations for voltage with a transistor being the other "resistor."

Example of a simple voltage divider as I understand it:

Imagine two 1k resistors in series. One end of the pair is connected to the positive rail and the other end to the negative rail. The voltage source is a 9V battery.

2k = R
9 = V

I = V/R

I = 4.5mA

Now get the voltage drop of each resistor...


V(Drop R1) = 4.5ma(1k)

V(Drop R1) = 4.5V

9V - 4.5V = V(Drop R2)

V(Drop R2) = 4.5V

So, you get 4.5V in between the two resistors.

 

That's true for the resistor connected to the transistor collector.
The resistor connected to the base is always connected.

When the circuit is operating, the capacitor is being peridically charged and discharged.
If the voltage across a capacitor is constant than the capacitor won't charge or discharge. But any change in the voltage across it will cause a charge flow.
---------------------------------------------
Let's take another shot at the simulation with different parameters displayed:

Below shows the voltage at the collector of Q2 [V(c2)], the voltage across capacitor C2 [V(C2)-V(B1)], the voltage at Q1's base [V(b1)] and the current through C2 [I(C2)].

Note the positive spike of current (positive is current from left to right) as the capacitor is charged when V(c2) goes high (the current on the right of the capacitor goes through Q1's forward biased base).

During the time V(C2) is high there no voltage change across the capacitor and thus no further capacitor current.

When V(C2) goes low there is a short negative spike due to stray circuit capacitances (primarily the charge from the base of Q1). This is small so has a negligible effect on the capacitor charge or voltage.
Note that the positive to negative transition at V(C2) is coupled directly through C2 to the base of Q1 (V(b1) but there is no significant change in voltage across the capacitor (since little charge flows during the transition).

During the time V(C2) is low the capacitor slowly discharges through R3 [voltage across R3 being the V1 supply minus V(b1)] which is the small I(C2) negative capacitor current.
No current goes through Q1's base since it is now reverse biased.

When the voltage across C2 becomes low enough, V(B1) becomes sufficiently high to forward bias Q1's base, turning it on and causing the circuit to flip to its other state.

Hope that helps your understanding a little.
Do you have any questions about that?

View attachment 86480

Okay. That helped a little. Let's see if I have this now...

Assume Q2 turns on first through R4. R4 limits current to a safe level on B2. The side of R4 connected to Q2's base is NOT electrically common with ground. It is Q2's EMITTER that is electrically common with ground. So, 9V at a safe current is applied to Q2's base.

Current limited by R1 at 9V is going from Q2's collector to its emitter. It is not the bottom of R1 that is electrically common to ground...it is Q2's emitter.

The current through R1 charges the left plate of C2. (This next part I think I might be wrong about.) The right plate of C2 goes negative because the positive charge on the left plate of C2 is stronger than the positive charge on the right plate. Since like charges are repelled, the left side of C2 wins and the electrons on C2's right plate are repelled into the base of Q1 and into ground. This is not violating the PN junction "diode" in Q1. Now the right plate of C2 is negative, keeping Q1 off.

During this time R2 is not connected to ground in anyway other than across C1. The right plate of C1 starts charging positively through R2 causing an opposite negative charge on the left plate due to a similar event as in the explanation for C2. This negative charge eventually overcomes the 9V on Q2's base through R4 and turns Q2 off. Then we have the "flop" and the events I just described are reversed.

Wrong? Right?

 

.......................
The current through R1 charges the left plate of C2. (This next part I think I might be wrong about.) The right plate of C2 goes negative because the positive charge on the left plate of C2 is stronger than the positive charge on the right plate. Since like charges are repelled, the left side of C2 wins and the electrons on C2's right plate are repelled into the base of Q1 and into ground. This is not violating the PN junction "diode" in Q1. Now the right plate of C2 is negative, keeping Q1 off.
.........................

I don't really understand what you are saying.
There is no "win" with a capacitor, only the relative voltage change across a capacitor and the charge that flows from that change.

If you are using conventional current flow (positive voltage to negative voltage), and not electron flow, then we use hypothetical positive charged carriers. Do no add electrons into the mix or you will become hopelessly confused.
Thus if you apply a positive voltage to one side of a capacitor then it forces the (hypothetical) positive charge out the other side.

The right of C2 goes negative when Q2 turns ON not OFF.
When Q2 turns OFF then the (conventional) current flows from R1 through C2 and into Q1's base.
Both the right and left side of C2 are positive with respect to ground under that condition.

Look at the simulation. If what you postulate is contrary to the simulation, then it's incorrect.

 

I don't really understand what you are saying.
There is no "win" with a capacitor, only the relative voltage change across a capacitor and the charge that flows from that change.

If you are using conventional current flow (positive voltage to negative voltage), and not electron flow, then we use hypothetical positive charged carriers. Do no add electrons into the mix or you will become hopelessly confused.
Thus if you apply a positive voltage to one side of a capacitor then it forces the (hypothetical) positive charge out the other side.

The right of C2 goes negative when Q2 turns ON not OFF.
When Q2 turns OFF then the (conventional) current flows from R1 through C2 and into Q1's base.
Both the right and left side of C2 are positive with respect to ground under that condition.

Look at the simulation. If what you postulate is contrary to the simulation, then it's incorrect.

It seems to match. (I think)

I think that the thing I'm having an issue with now is why exactly the right side of C2 becomes negative. I understand that positive charge on one side of a capacitor means negative charge on the other.

Both sides of C2 are connected to 9v. The current coming through R3 is less than the current coming through R1...is that why?

 

It seems to match. (I think)

I think that the thing I'm having an issue with now is why exactly the right side of C2 becomes negative. I understand that positive charge on one side of a capacitor means negative charge on the other.

Both sides of C2 are connected to 9v. The current coming through R3 is less than the current coming through R1...is that why?

Okay, yes. Perhaps the light is starting to come on.

But note that looking at capacitor charge as both positive and negative tends to confuse the issue. Pick one polarity of charge and stick with it. For conventional current flow you use positive charge.
Thus a positive voltage applied to one side of the capacitor will transfer (positive) charge into that terminal and positive charge out the other terminal.

Since R3 is 50 times larger than than R1 that means the current is 50 times smaller for the same voltage across it.

The right side of C2 becomes negative when Q2 turns on and brings the left side of C2 from V+ to 0V.
Since the right side of C2 is only about 0.7V when that occurs, this negative going voltage is coupled by the capacitor from the left to the right.
The right side of the capacitor thus goes from 0.7V to about -4.5V (for a 5V supply).

The important thing to keep in mind is that the voltage across a capacitor cannot change without the transfer of charge.
So, say you have a capacitor charged to 5V across its terminals.
If the positive terminal is connected to +5V then the other terminal will be at ground voltage (0V).
If the positive terminal is connected to ground (0V) then the other terminal will be at -5V with respect to ground.
For either case the voltage across the capacitor is unchanged at 5V.

Make sense?

 

So, you get 4.5V in between the two resistors.

This why on earth do you think a single resistor drops the TOTAL vcc when there is a transistor between it and ground? Surly you must know that the transistor drops something. In fact, the transistor drops the total vcc when cutoff, and about .2v when in saturation. Either way, the low end of a resistor is NEVER negative, unless you are operating with a negative (ie split) power supply.

 

This why on earth do you think a single resistor drops the TOTAL vcc when there is a transistor between it and ground? Surly you must know that the transistor drops something. In fact, the transistor drops the total vcc when cutoff, and about .2v when in saturation. Either way, the low end of a resistor is NEVER negative, unless you are operating with a negative (ie split) power supply.

I was under the impression that a transistor which was on acted as a wire...my mistake...

I also didn't know that the collector-emitter junction caused a voltage drop, my mistake. I'm wondering why it would drop any voltage...if the only thing keeping it from being a "wire" is the P slice in the middle and that is taken care of by current at the base it seems it shouldn't have a voltage drop.

I'm inexperienced. It's not as if I'm trying to be difficult or brick-headed.

 

Okay, yes. Perhaps the light is starting to come on.

But note that looking at capacitor charge as both positive and negative tends to confuse the issue. Pick one polarity of charge and stick with it. For conventional current flow you use positive charge.
Thus a positive voltage applied to one side of the capacitor will transfer (positive) charge into that terminal and positive charge out the other terminal.

Since R3 is 50 times larger than than R1 that means the current is 50 times smaller for the same voltage across it.

The right side of C2 becomes negative when Q2 turns on and brings the left side of C2 from V+ to 0V.
Since the right side of C2 is only about 0.7V when that occurs, this negative going voltage is coupled by the capacitor from the left to the right.
The right side of the capacitor thus goes from 0.7V to about -4.5V (for a 5V supply).

The important thing to keep in mind is that the voltage across a capacitor cannot change without the transfer of charge.
So, say you have a capacitor charged to 5V across its terminals.
If the positive terminal is connected to +5V then the other terminal will be at ground voltage (0V).
If the positive terminal is connected to ground (0V) then the other terminal will be at -5V with respect to ground.
For either case the voltage across the capacitor is unchanged at 5V.

Make sense?

I think so. I think later in the evening tomorrow I'll try building one with my own values and see if I can predict the output.

After my expiriment I'm sure I'll have plenty more questions. Thanks!

 

I was under the impression that a transistor which was on acted as a wire...my mistake...

I also didn't know that the collector-emitter junction caused a voltage drop, my mistake. I'm wondering why it would drop any voltage...if the only thing keeping it from being a "wire" is the P slice in the middle and that is taken care of by current at the base it seems it shouldn't have a voltage drop.

I'm inexperienced. It's not as if I'm trying to be difficult or brick-headed.

You make ALOT of assumptions, most of them bad. The P-region is definitely NOT the only thing keeping a transistor from being a wire. I suggest you learn about electronic components instead of making assumptions about them. A transistor operating in the active region exhibits constant current at it's collector lead. So, if we designate constant collector current is IC, then a single resistor connected between VCC and a transistor's collector will have a voltage drop of IC*R. EG: a 1k ohm resistor and IC = 10 mA, VR = 10V. And so if VCC = 15V, VCE = 5V.