D1 is backwards.

This looks promissing. The first output pulse is sufficiently long to suppress the one at 700µS as requested. But at the following trigger at 1mS gives a short output pulse. What is the cause. C not completely discharged? Is there a solution?

 

If you want to trigger an output pulse with a negative input, you can do it with a comparator. But it might not be what you need because I dont know the requirements for your assignment. This is my approach if I understand correctly, which is different but if you want you can read it

When the comparator gets on its positive input (U+) a voltage of "-10V" and on its negative input (U-) a voltage of "-12V" it will output the power supply for the positive input. You put on the positive power supply "5V" and you will get "5V" on the output when the positive input (U+) is higher.

With 2 operational amplifiers you can inverse the "-10V" so they can become "+10V" then output them on a second operational amplifier wired as a schmit trigger. That way the schmit trigger will output "5V" when it gets "10V" on the input and until the voltage on the input drops from "10V" to whatever is the lower border, it will pass "1ms" or as much as you want.

Or you could invert the voltage to "10V" input it to a comparator with "5V" and "0V" power supply and just keep it on for as long as you want with a "555 timer" or any multivibrator.

 

Hello, Thanks for info. Is the inversion of the -10 to +10 feasible with one power supply? and how would you realise it?

 

You have to try with 1 power supply of "+10V" only on the positive power supply.

This is what orcad gives me with 2 power supplies (+-10V). You can try with 1.

EDIT: the "9.3" is the voltage.

 

The first output pulse is sufficiently long to suppress the one at 700µS as requested. But at the following trigger at 1mS gives a short output pulse. What is the cause. C not completely discharged? Is there a solution?

Read post #13.

ak

 

Read post #13.

ak

Do you mean that the circuit will only function as requested after the specified time?
In fact it should function from the first pulse...

 

The negative-going transition level of a 4093 is Vdd/3

Are you thinking of a 555? According to TI's 4093 datasheet "Hysteresis voltage typically 0.9V at Vdd=5V and 2.3V at Vdd=10V". So the typical transition levels are about 40% and 60% of Vdd.

 

Alec is correct. I wasn't thinking of the 555, I was scrambling with bad memory.

ak

 

Do you mean that the circuit will only function as requested after the specified time?
In fact it should function from the first pulse...

Normally, the circuit powers up with C2 completely discharged. At the end of the first output pulse, C2 is charged up to approx. 60% of Vdd. This has to be discharged if the next pulse is to be as long as the first. If you know that the minimum time between trigger events is less than 5 times the output pulse width, then the next pulse will be short.

ak

 

Normally, the circuit powers up with C2 completely discharged. At the end of the first output pulse, C2 is charged up to approx. 60% of Vdd. This has to be discharged if the next pulse is to be as long as the first. If you know that the minimum time between trigger events is less than 5 times the output pulse width, then the next pulse will be short.

ak

Thanks for info, but as stated, circuit should function correctly from first pulse. Pulses normally come every 135mSec; some can be double as in my PWL and those second ones have to be ignored.

 

135 ms or 135 us? Can you post a sketch of the input waveform timing with both normal and error conditions?

ak

 

135 ms or 135 us? Can you post a sketch of the input waveform timing with both normal and error conditions?

ak

Hello, in included JPG:
The amplitude on the JPG: one cell is 5V high.
Typical situation is 1 large and good (first) and 3 smaller pulses (to be ignored), then again one good and 3 to ignore...(continues like that). (But there is only one more of them showed on this JPEG)
As you can see the difference between a good one and a bad one is not always as big as between pulse one and pulse 2-3-4. e.g. pulse 5 (=OK) and 6 (to be ignored) .
(The 3 smaller ones are in fact RFI)
I'll also put a trim pot at the entry of first Op Amp to attenuate to the right level or change the ref level.
The timing: intervals will be about 4 times longer as on the JPG since the JPEG is a running engine at RPM 880, and the circuit will have to function at about RPM 250 (cranking). So the lock out should be about 135mS (and i'll have to include a potmeter for adjustment of the lenght of the lockout).
The OUT pulse be can the same length as the lockout time if this is easier to realise.