Hi, I'm recently working on designing a one-bit full adder with 9 transistors.
Below are the schematic and the HSPICE code I used to run the simulation.
For COUT(inverted twice) :
For SUM(inverted twice) :
So, the problem is that at input tuples (a, b, cin) = (0, 0, 0) & (0, 1, 1) the sum is obviously wrong.
But I can't fix it. I've tried to adjust the width of the MOS in the path of these two tuples, but in vain.
BTW, I'm designing this in a 0.18um technology.
Can anyone help me with this?
Thanks in advance!!
Below are the schematic and the HSPICE code I used to run the simulation.
And here is the result waveform in nWave*.ONEBIT_FULLADDER
**--------**
** Set-up **
**--------**
.lib "umc018.l" L18U18V_SS
.param supply = 1.8v
.param C_load = 10fF
.global VDD GND
.TEMP 25
.op
.options post
.param length = 0.18u
**---------**
** Sources **
**---------**
v1 VDD GND supply
v2 a GND PULSE(0v 1.3v 2ns 0.1ns 0.1ns 1.0ns 2.4ns)
v3 b GND PULSE(0v 1.3v 3.2ns 0.1ns 0.1ns 2.2ns 4.8ns)
v4 cin GND PULSE(0v 1.3v 5.6ns 0.1ns 0.1ns 4.6ns 9.6ns)
**----------**
** Circuits **
**----------**
X1 a b cin 1 2 FA
X2 1 sum_inv INV
X3 sum_inv sum INV
X4 2 cout_inv INV
X5 cout_inv cout INV
C1 sum_ff GND C_load
C2 cout_ff GND C_load
* FULL_ADDER *
.subckt FA
+INA INB CIN SUM COUT
X1 INA INB 1 XOR
X2 1 INA CIN COUT TWO2ONE_MUX
X3 COUT 2 INV
mp SUM 1 CIN CIN P_18_G2 w=0.18u l=length
mn SUM 1 2 2 N_18_G2 w=0.18u l=length
.ends
* XOR Gate *
.subckt XOR
+IN1 IN2 OUT
mp1 OUT IN1 IN2 IN2 P_18_G2 w=0.36u l=length
mp2 OUT IN2 IN1 IN1 P_18_G2 w=0.9u l=length
mn1 OUT IN1 GND GND N_18_G2 w=0.18u l=length
.ends
* 2_to_1_MULTIPLEXER *
.subckt TWO2ONE_MUX
+SEL IN1 IN2 OUT
mp OUT SEL IN1 IN1 P_18_G2 w=0.54u l=length
mn OUT SEL IN2 IN2 N_18_G2 w=0.54u l=length
.ends
* INVERTER *
.subckt INV
+IN OUT
mp OUT IN VDD VDD P_18_G2 w=0.18u l=length
mn OUT IN GND GND N_18_G2 w=0.18u l=length
.ends
.end
For COUT(inverted twice) :
For SUM(inverted twice) :
So, the problem is that at input tuples (a, b, cin) = (0, 0, 0) & (0, 1, 1) the sum is obviously wrong.
But I can't fix it. I've tried to adjust the width of the MOS in the path of these two tuples, but in vain.
BTW, I'm designing this in a 0.18um technology.
Can anyone help me with this?
Thanks in advance!!