Hey guys.... I have a Memory Cell for RAM like the one in the first picture....I want to understand the reading concept...so on the SELECT line a signal is coming (in fact is the ADDRESS decoded from the second picture) , I guess that the INPUT DATA is zero because I want to read the information...what I don't understand is why READ is on the same line as WRITE (if I have a single line I can trasmit only one bit, right? so 0 is nothing and 1 for example is reading...what code do I have for writing??....and another question ... the READ/WRITE is coming on the Control Bus from the Processor? )
Please if you can explain me a little bit the flow of the bits inside these cells.

 

READ is on the same line as WRITE.

Did you notice the line over the label WRITE?

This means that READ is positive logic while WRITE is negative logic.
It also means that when READ = FALSE, WRITE = TRUE.

In summary, when you are NOT WRITEing you are READing.

 

READ is on the same line as WRITE.

Did you notice the line over the label WRITE?

This means that READ is positive logic while WRITE is negative logic.
It also means that when READ = FALSE, WRITE = TRUE.

In summary, when you are NOT WRITEing you are READing.

Thank you Sir....but READ/WRITE is coming through the Control Bus from the Processor?

 

Thank you Sir....but READ/WRITE is coming through the Control Bus from the Processor?

So? What's your question?

 

Yes, The proccesor will be in control of all data transfers and it is the proccesor that knows if it is about to read or write data. After the read/NOT write (The bar above write means NOT) and address signals are stable the memory enable signal will be asserted which for a read will enable tri state drivers to put the data on the bus which the proccesor will read. For a write the proccesor will have already put the data on the bus and the memory enable signal will cause the memory to write that data into the selected location.

Les.

 

Yes, The proccesor will be in control of all data transfers and it is the proccesor that knows if it is about to read or write data. After the read/NOT write (The bar above write means NOT) and address signals are stable the memory enable signal will be asserted which for a read will enable tri state drivers to put the data on the bus which the proccesor will read. For a write the proccesor will have already put the data on the bus and the memory enable signal will cause the memory to write that data into the selected location.

Les.

Both the Memory Enable signal and READ/NOT WRITE signal are coming through the Control Bus?

 

Both the Memory Enable signal and READ/NOT WRITE signal are coming through the Control Bus?

Yes and yes.