How to Design two decade counters that are cascaded to produce an output from 00 to 99 on 8 digital outputs. Also to Arrange an input that can stop the count when brought low – use a switch on the development board for this purpose. Drive this design from your 1 Hz source.


Any Suggestion would be helpfull....

Thanks
KJ

 

Get a data sheet for a 74162 and look at the internal logic. Pretty simple.

 

Found the datasheet....please advice

http://pdf1.alldatasheet.com/datasheet-pdf/view/27441/TI/74162.html

 

Page 9 of the datasheet shows how to arrange a BCD counter. Just ignore the parallel load logic. Pay attention to how the logic stops the count at 9 rather than F.

If you can't use a counter IC, then you can use standard logic to duplicate the function.

 

This is what I did in Quartus II....this BCD counter counts from 0-9 and then resets.....Please advice.....

 

Then you need another one to count from 10 to 90.

 

Then you need another one to count from 10 to 90.

You mean I will need to draw another one of them.....?
How do I join them.....

Thanks
KJ

 

The idea is that ANDing the outputs for '9' and the clock take the state back to 0. For the next stage, the previous state of '9' and a clock should advance the count.