I have a Texas Instruments DAC8806 in my FPGA circuit. It is a parallel in and analog out device. Info can be found from DAC8806.pdf. I am having trouble understanding the pdf. In this description on page(s) 4 and 13, it talks about LDAC, WR, and DATA. On page 13, there is a diagram and an explanation. They do not appear to be the same. My understanding of timing diagram is the following:
Please excuse the format, it should run like VHDL
Each clock is 10ns
On a clk rising edge, do the following
clk = clk + 1
If clk = 20 then
write data to pins on chip.
If clk = 25 then
WR = '0' " Puts data into input register on chip"
if clk = 30 then
WR = '1'
if clk = 35 then
LDAC = '1' " Puts data from input to DAC register
If clk > 40 then
clk = 0 "reset clk counter"
LDAC = '0'
Per the pdf, is my logic correct?
Please excuse the format, it should run like VHDL
Each clock is 10ns
On a clk rising edge, do the following
clk = clk + 1
If clk = 20 then
write data to pins on chip.
If clk = 25 then
WR = '0' " Puts data into input register on chip"
if clk = 30 then
WR = '1'
if clk = 35 then
LDAC = '1' " Puts data from input to DAC register
If clk > 40 then
clk = 0 "reset clk counter"
LDAC = '0'
Per the pdf, is my logic correct?
