# Need help in designing Unusual Clock dividers with and without 50% duty cycle

#### sharanyakhamithkar

Joined May 18, 2015
5
How to design the following unusual clock dividers and plot the timing diagrams using Cadence or Spice tool?
1 A glitch free odd integer clock divider with 50% duty cycle.
2 A glitch free non-integer clock divider with 50% duty cycle.
3 A glitch free non-integer clock divider without 50% duty cycle.

#### MrChips

Joined Oct 2, 2009
24,236
We do not do your homework for you. Show use your efforts and then we can guide you.

#### sharanyakhamithkar

Joined May 18, 2015
5
thank you.
if you can, please give me any material related to this topic.
i have no idea to do.
just suggest me how to do.
i ll try and let you know, if i struck somewhere, please suggest me.

thank you.

#### Papabravo

Joined Feb 24, 2006
16,833

#### WBahn

Joined Mar 31, 2012
26,398
Have you even attempted to look for information on this? There is a LOT of stuff out there. Just Google "non-integer clock divider" and you will get a bunch. Read up on that, then show YOUR best attempt to solve YOUR homework problem. That gives us a starting point for discussion.

#### sharanyakhamithkar

Joined May 18, 2015
5
To be frank, i didn't try. Because i've time for it. Now we have exams, after that i need to do this assignment. I just thought of asking your suggestions. anyways Thanks!! I will try and let you know.

#### sharanyakhamithkar

Joined May 18, 2015
5
I've tried to get odd integer (3) clock divider using flip-flops and few logic gates, I've got partial output as shown in attached file.
I'm getting correct output only in positive pulse and its following the input in negative pulse. What can be the problem?

#### Attachments

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#### Alec_t

Joined Sep 17, 2013
12,215
Post a schematic showing how the flip-flops and gates are connected.

#### WBahn

Joined Mar 31, 2012
26,398
I've tried to get odd integer (3) clock divider using flip-flops and few logic gates, I've got partial output as shown in attached file.
I'm getting correct output only in positive pulse and its following the input in negative pulse. What can be the problem?
We can't tell much if we don't see your schematic. There are pretty much an infinite number of circuits that will give a particular waveform, so don't make people guess what you have done.

#### sharanyakhamithkar

Joined May 18, 2015
5
Problem solved!
I've got 50% duty cycle, by changing D-latch to Master-Slave D Flip-flop.

anyhow, thank you!

#### WBahn

Joined Mar 31, 2012
26,398
Do you understand why switching to a master-slave flip flop worked? Or was that just "a happening" -- meaning that you tried something and it just happened to work? I suspect it is the latter because if you made the change deliberately, you would have seen that you could have solved the problem (most likely, since we still haven't seen your circuit) with an inverter.