I have this problem where I have to build a serial transmission system using 74195 chips, that allows for 8bits of register Y to be transfered serially to 8 bit register Z. A clock is available to both devices. The transfer should not destroy Y's register contents and should stop after those 8 bits are transfered, even if the clock continues ticking. Y register has 3 operations: Clear, transfer to register Z, and load from DO0-DO7. While register Y has 3 operations, register Z only has one operation which is to accept the data from Y. I am the controller of both clock and combined control.

This is what I have designed so far in logik works. Any help and explanations are appreciated. I am not sure if what I currently have is correct. Thanks.

 

It's the stuff off-stage that you need to work on. How will the clock source know when to run, and for how long? When does the CLEAR function operate?

It is hard to follow your "I am the controller". Does that mean you manually clock and clear the data? If so, what results are you getting?

 

Let's break the problem down:

You need to serially transfer the 8 bits of data from Y to Z. Take a look at the data sheet. AllDataSheet.com is my favorite place for data sheets (http://pdf1.alldatasheet.com/datasheet-pdf/view/12637/ONSEMI/74LS195.html). Study the Functional Description section closely.

You will also need more ICs -- for the clock & a counter to start and stop the clocks to the '195s.

There is more breaking down that is needed, but concentrate first on the parallel-to-serial portion first.

--Rich