In post #6 @ericgibbs pointed out that for an unconnected input, the output of CMOS could either be low or high. The output of TTL would be high for an unconnected input.

Unknown, usually called "Don't Care" and unconnected are ***not*** the same thing. All inputs to logic gates must be terminated to a high or low state. They just must. We can go through another 18 posts, but the answer will not change.

In post #16 I tried to address it indirectly. I'm sorry that I should have provided more content for the question. I agree that in digital logic, "x" is a don't care condition. In the context of Verilog, it's an unknown condition. That table was taken from a Verilog book. Also check this: https://stackoverflow.com/questions/49987012/the-difference-between-x-and-z

"Don't care" may also refer to an unknown value in a multi-valued logic system, in which case it may also be called an X value or don't know.[16] In the Verilog hardware description language such values are denoted by the letter "X". In the VHDL hardware description language such values are denoted (in the standard logic package) by the letter "X" (forced unknown) or the letter "W" (weak unknown).[17]

https://en.wikipedia.org/wiki/Don't-care_term#X_value

According to the Wikipedia article given below, for a multi-values logic system (whatever it is?), the "x" could be an unknown value as well.

Thank you!

 

You can say:
x NAND 0 = 1
x NAND 1 = not x
if you want, but I don’t think it would be very useful.

 

I agree that in digital logic, "x" is a don't care condition. In the context of Verilog, it's an unknown condition. That table was taken from a Verilog book.

FINALLY, enough information to answer the original question:

Yes.

ak

 

I think the following truth table is correct.
View attachment 267956

Try using Boolean algebra to solve the logic function instead of trying to imagine an input in some unknown state. If you can ensure that an input signal is either pulled high to logic 1 or pulled low to logic 0 with a resistor or some other means of never leaving an input floating, then the algebraic models of logic gates will probably be sufficient.

 

Try using Boolean algebra to solve the logic function instead of trying to imagine an input in some unknown state.

Agreed, no need to invoke Schrödinger’s cat here. It‘s not quantum physics!

 

Thank you, everyone!

By the way, shouldn't all digital system be started with RESET input(s) so that the system starts in a known state?

Assuming the answer to what I asked above is 'yes', what RESET CMOS systems use? Active LOW or Active HIGH? Or, it doesn't matter; it could be either Active LOW or Active HIGH?

 

Only sequential logic (i.e. that which has a clock signal which causes it to change state) requires a reset signal.

 

Look at the datasheets for 20 different flipflops, counters, and shift registers, and you will see many ways a Reset function can be implemented.

Some counters have a synchronous Reset - the counter is not reset the instant the Reset input is asserted; it waits until the next clock pulse. That can be fun.

ak