Assuming input of bottom transistor (NMOS) of NAND gate is held at VDD and upper transistor (NMOS) switches from 1-0 , what should be the current equation that must be substituted for Isub in the equation delay= C*V/Isub ..
As per my knowledge, one of the PMOS transitors will be conducting and the output charges through PMOS and hence Isub= Isub(PMOS).
But in the paper attached, they have mentioned the currents (CASE 2) only in terms of NMOS.. On what basis is the analysis of NAND gate currents done in the attached paper..?
And also for the state 00, i have come accross few papers which specify current= 2*ileak and few cuurent= ileak..it is contradicting and the same ambiguity for state11...what is the exact analysis for this..?
http://ece.uwaterloo.ca/~elmasry/papers/076.pdf
https://www.springer.com/cda/conten...1963871-c1.pdf?SGWID=0-0-45-963465-p173994674 (page 35)
As per my knowledge, one of the PMOS transitors will be conducting and the output charges through PMOS and hence Isub= Isub(PMOS).
But in the paper attached, they have mentioned the currents (CASE 2) only in terms of NMOS.. On what basis is the analysis of NAND gate currents done in the attached paper..?
And also for the state 00, i have come accross few papers which specify current= 2*ileak and few cuurent= ileak..it is contradicting and the same ambiguity for state11...what is the exact analysis for this..?
http://ece.uwaterloo.ca/~elmasry/papers/076.pdf
https://www.springer.com/cda/conten...1963871-c1.pdf?SGWID=0-0-45-963465-p173994674 (page 35)
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