Hi All
I've been on a bit of a crash course learning about FETs, and, yes, I'm hoping for some more great pointers .
Consider the simple circuit shown in attached circ1.png, i.e., a N-channel logic-level MOSFET that switches the voltage being delivered to a voltage buffer. I am trying to understand more about the peaking shown in the voltage signal.
With high values of R1 the peaking, or overshoot, becomes much more pronounced (Ids is also higher) than at lower levels of R1 (Ids lower). Am I right in thinking that R1 is 'working' with the capacitance of the MOSFET to create a pole in the system that causes this peaking, or is something else at play?
How does one usually attempt to minimize this peaking? I have read about using small gate resistances on the MOSFET to slow the rise time, and also about impedance matching. Are these applicable in this situation?
Thanx!!!!
I've been on a bit of a crash course learning about FETs, and, yes, I'm hoping for some more great pointers .
Consider the simple circuit shown in attached circ1.png, i.e., a N-channel logic-level MOSFET that switches the voltage being delivered to a voltage buffer. I am trying to understand more about the peaking shown in the voltage signal.
With high values of R1 the peaking, or overshoot, becomes much more pronounced (Ids is also higher) than at lower levels of R1 (Ids lower). Am I right in thinking that R1 is 'working' with the capacitance of the MOSFET to create a pole in the system that causes this peaking, or is something else at play?
How does one usually attempt to minimize this peaking? I have read about using small gate resistances on the MOSFET to slow the rise time, and also about impedance matching. Are these applicable in this situation?
Thanx!!!!
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