I am wondering about the topic Maximum Via Stub Length. I have heard about it but to be honest have not looked more in to that stuff. Is there a maximum length of the via stub that ensures no reflection and we are fine to have them and leave them without back drill ?

 

I am wondering about the topic Maximum Via Stub Length. I have heard about it but to be honest have not looked more in to that stuff. Is there a maximum length of the via stub that ensures no reflection and we are fine to have them and leave them without back drill ?

Unless your signal speed is so high (10 gbps+) that stubs (as a 1/4 wavelength conductor) become transmission line elements I wouldn't worry.

https://www.google.com/url?sa=t&sou...4QFnoECC8QAQ&usg=AOvVaw2UbDE5cwsf6KMQgMHV-hme

 

and how do we calculate in nummers as a function of bps ?

 

and how do we calculate in nummers as a function of bps ?

Do you really need to ask that?

Hz=Bps/N

Frequency in Hertz (Hz) = 500
Data transmission rate in bits per second (Bps) = 1000
Number of bits per cycle (N) = 2

 

Sorry I mean how to calculate maximum length of stub as a function of bps.

 

Sorry I mean how to calculate maximum length of stub as a function of bps.

https://www.edn.com/how-long-a-stub-is-too-long-rule-of-thumb-18/

Unless you're designing for 10's of GHz signals, the small transmission discontinuity from a stub is a very small signal effect.

 

Sorry I mean how to calculate maximum length of stub as a function of bps.

It's not the pbs of a digital signal that's important here, it's the pulse rise and fall times that determine whether line reflections may be a problem.
The general rule is that, if the propagation time of the trace length is more than 25% of the signal rise/fall time, then significant transmission line effects will be seen.

So what is the rise/fall time of your signal?

 

Transmission line effects will be seen but might not be important at lower speeds IRT with a Via Stub length.

Bps and rise/fall times are both important. If the transmission line effects don't cause issues at the sampling point (usually in the middle of the pulse) then purely from signal integrity, fast rise/fall times are less important because they happen only at the ends of the cycle, not at digital clocked logic signal sampling points.
https://download.ni.com/evaluation/pxi/Digital_Timing.pdf

 

Here's an example of transmission line effects seen but not important for signal integrity. You can easily see the rise/fall time in relationship to bps.



I'm scoping the 15MHz SPI clock signal to the GLCD display. Yellow: at the board connector, Green: at the display connector.

The signal integrity improvement solution at the display connector end is a simple series resistor as seen in this GLCD prototype board.
It will run a 15MHz without the resistor but I wanted a better signal at the display with a 30MHz clock.

https://resources.altium.com/p/damping-and-reflection-transfer-series-termination-resistor

 

...then purely from signal integrity, fast rise/fall times are less important because they happen only at the ends of the cycle, not at digital clocked logic signal sampling points.

I don't agree at all. I'm curious... how do you know the signal you're talking about isn't a clock signal (ie the SPI clock), where an extra transition caused by poor signal integrity would be a disaster? When is the "sampling point"?

What you say might be true for an async signal that's sampled, otherwise but rise/fall times can be VERY important as they're typically much higher than the base signal freq and if you don't have the bandwidth for them to propagate undistorted then the signal integrity suffers.

 

I don't agree at all. I'm curious... how do you know the signal you're talking about isn't a clock signal (ie the SPI clock), where an extra transition caused by poor signal integrity would be a disaster? When is the "sampling point"?

What you say might be true for an async signal that's sampled, otherwise but rise/fall times can be VERY important as they're typically much higher than the base signal freq and if you don't have the bandwidth for them to propagate undistorted then the signal integrity suffers.

ME

Bps and rise/fall times are both important.

It's called building the board and understanding the details of every chip, component and interconnect requirement, that's how I know what type of signal to design for. If it's a async edged triggered signal vs synchronous clocked design then there are different rules for the design but the engineer of the PCB will or should know that. https://en.wikipedia.org/wiki/Sequential_logic

Asynchronous (clockless or self-timed) sequential logic is not synchronized by a clock signal; the outputs of the circuit change directly in response to changes in inputs. The advantage of asynchronous logic is that it can be faster than synchronous logic, because the circuit doesn't have to wait for a clock signal to process inputs. The speed of the device is potentially limited only by the propagation delays of the logic gates used.

However, asynchronous logic is more difficult to design and is subject to problems not encountered in synchronous designs. The main problem is that digital memory elements are sensitive to the order that their input signals arrive; if two signals arrive at a flip-flop or latch at almost the same time, which state the circuit goes into can depend on which signal gets to the gate first. Therefore, the circuit can go into the wrong state, depending on small differences in the propagation delays of the logic gates. This is called a race condition. This problem is not as severe in synchronous circuits because the outputs of the memory elements only change at each clock pulse. The interval between clock signals is designed to be long enough to allow the outputs of the memory elements to "settle" so they are not changing when the next clock comes. Therefore, the only timing problems are due to "asynchronous inputs"; inputs to the circuit from other systems which are not synchronized to the clock signal.

I agree they CAN be VERY important. With synchronous systems the sampling point state flows are aligned to a clock signal, it's important for that clock to be as undistorted as possible. That's why I used damping resistors in the GLCD design with a solid ground plane on the production board. SPI is a synchronous interface.

https://www.csun.edu/edaasic/roosta/Syn_Asyn_Design.pdf

With all of the potential advantages of asynchronous circuits, one might wonder why synchronous systems predominate. The reason is that asynchronous circuits have several problems as well: Asynchronous circuits are more difficult to design in an ad hoc fashion than synchronous circuits. In a synchronous system, a designer can simply define the combinational logic necessary to compute the given function, and surround it with latches. By setting the clock rate to a long enough period, all worries about hazards (undesired signal transitions) and the dynamic state of the circuit are removed. In contrast, designers of asynchronous systems must pay a great deal of attention to the dynamic state of the circuit. Hazards must also be removed from the circuit, or not introduced in the first place, to avoid incorrect results. The ordering of operations, which was fixed by the placement of latches in a synchronous system, must be carefully ensured by the asynchronous control logic. For complex systems, these issues become too difficult to handle by hand.

The object of good digital PCB design is not to get perfectly undistorted signals with perfectly fast rise/fall times in the vast majority of cases. There is usually a compromise that delivers a signal well within the needed specifications.
https://www.eetimes.com/rise-time-signal-integrity/

 

Hi again, we actually are working with 10 Gbps. How do I know about rise/fall time of a digital signal with bit rate 10 Gbps ?

I understand that the rise/fall time define the bandwidth. In order to calculate the wavelength, we need the bandwidth of the signal and the speed of signal in the PCB. Then we can calculate the 1/4 wavelength.

But how do we relate 10 Gbps to the rise/fall time ?
If the length of the via stub is less then 1/4 wavelength would that be ok to leave it without back drilling or without terminated if this is trace stub ?

 

Hi again, we actually are working with 10 Gbps. How do I know about rise/fall time of a digital signal with bit rate 10 Gbps ?

I understand that the rise/fall time define the bandwidth. In order to calculate the wavelength, we need the bandwidth of the signal and the speed of signal in the PCB. Then we can calculate the 1/4 wavelength.

But how do we relate 10 Gbps to the rise/fall time ?
If the length of the via stub is less then 1/4 wavelength would that be ok to leave it without back drilling or without terminated if this is trace stub ?

Look at the AC specifications of the device pins sourcing the signal.
For example: https://ww1.microchip.com/downloads.../OTH/ProductDocuments/DataSheets/sy58016l.pdf

https://experience.molex.com/bytes-bits-frequencies-and-rise-time/

A formula often found in the literature is

Rise time (in nanoseconds) = 0.35/bandwidth (in GHz)
or
Bandwidth (in GHz) = 0.35 / Rise time (in nanoseconds)

"And rise time is like pharmacy: more than needed is most of the time no good!"

PIC32 pin slew rate adjustments.
Medium slew rate 15MHz SPI clock and data. Yellow clock.

Clean eye, wide center opening.

Fastest slew rate for clock and data.

Much more messy.
As you can see, faster rise/fall times can actual reduce signal integrity by creating more high frequency harmonics. If the signal transmission line was perfectly matched it wouldn't be a problem but that's not usually the case.