Hi,

I am designing a DDR3 UDIMM module for PC for my own experimental interest. The config I am aiming for is 128*8 organization, 16 chips in total (dual rank, 8 DRAM chips per rank). I really put a lot of research for DDR3, including length matching, termination, signal routing etc. Approaching the end of my design I noticed that all my traces got really long... Dont get me wrong, from the physical point view, my design is really strong: each signal layer has ground reference planes both above and below, controlled impedance environment, minimal count of vias, every via has a ground via right next to it for return current, length matching, generous spacing to avoid crosstalk etc. The only thing that frightens me is that for data lane signals I have an overall length of 170 mm (150mm from connector to first rank chip, 20mm sections connect different rank chips) and 580mm length for a control signal group (from the connector, to termination beyond last chips), of course, the routing was done in strict fly-by topology.

I am not asking ,,will my design work?". I would like to know are there any theoretical transmission line length limitations for DDR3 beyond which I can not even expect it to work at the first place. Since the design is experimental, I am not aiming for some exact clock rate, I can go as low as 400 MHz, but this question is related to some really advanced physic and signal integrity knowledge, which I obviously lack. So any observations about maximum trace length to clock frequency relation (if any) would also be appreciated.

Short side question. As for my control group signals, there is initial 50 mm section from connector, to first DRAM chip, then every two neighboring chips are connected with 35 mm section, and a couple of mm for termination resistors at the end (in total 580 mm). I know that processor does some kind of timing skew training when I turn on my PC, purpose of which is to detect the natural time skew between control and data group signals, that is later accounted for. I have checked some application notes, but I can not find is there a maximum allowed time/length discrepancy for the signal groups?

Thank you in advance

 

Your DDR3 UDIMM design—with 170 mm data traces and 580 mm control traces—is definitely on the longer side, but that doesn’t mean it won’t work. There aren’t strict limits on trace length in the DDR3 spec, but longer traces introduce more delay and potential signal issues. In your case, you're looking at roughly 1 ns of delay for data and up to 4 ns for control signals. At speeds like DDR3-800, that’s pushing the timing limits most controllers are built to handle.

That said, since this is an experimental project and you're okay with running at lower speeds like DDR3-400, you’ve still got some flexibility. Most DDR3 controllers can handle a couple of nanoseconds of skew, especially with fly-by routing and proper training. From what you’ve described, your layout is solid in terms of signal integrity. If you’re using a controller with adjustable settings—like something FPGA-based—you’ll likely be able to get it working. Running a signal integrity simulation would be a smart next step, just to be sure.