max_pass circuit filters an array of 32 bits such that the blocks of bits 1 of maximum length remain on position and everything else becomes 0.

**A block/set is consisted of minimum 2 bits of 1.**

The circuit has to be combinational and the interface of the max_pass module is:

input array named "din" ->32bits

output array name "dout" ->32bits

The circuit has no memory. Output immediately sees any changes in input.

So, I have to implement this in Verilog, but first of all I need to find an algorithm.

**Examples**

Example 1

input: 01011100111111111111011100101010

output: 00000000111111111111000000000000

The maximum length of a block is 12.

Example 2

input: 00100111111001001011111100101101

output: 00000111111000000011111100000000

Two blocks of maximum length of 6.

Example 3

input: 11011011011011011011011011011011

output: 11011011011011011011011011011011

Eleven blocks of maximum length of 2.

Using Combinational Logic only!

What I`ve tried so far :

Using a MUX-DMUX circuit I can compare 2 numbers of 2 bits, let's say M,N and the function return 1 if M>N (it can be modified to return 1 if M=N=11 also ).

M=ab, N=cd.

I`m not sure how to find the maximum block.

I am in a learning process and any idea is welcome!

Thank you!