Hi could someone please help me with the following problem:
In class we have looked at the design of an equality compare module. For this problem you should design a magnitude compare module for 4 bit unsigned binary numbers. The module inputs are A[3..0] and B[3..0]. The two outputs are G and L, such that G is true iff A is greater than B; L is true iff A is less than B. (Thus if A == B, G and L are both false, and GL = 11 should never occur).
Where e means all stages to the right are equal, & E means this stage and all stages to the right are equal.
I figure the magnitude compare module must look similar with two compare blocks as above, but instead with four bit inputs.
My first block would have inputs A3, A2, A1, A0 and my second block would have inputs B3, B2, B1, B0.
The spec says there are two outputs G & L. So would each block contain both outputs or each block would contains one of each?
i.e. block one: G & L; block two: G & L
or block one: G; block two: L
???
I really am lost. I don't know exactly how a magnitude compare module differs from an equality compare module.
I first began this problem with a truth table.
After this, I got stuck and now I have no idea where to go from here.
Could someone please guide me with steps on what to do and how to implement this problem?
Any help will be greatly appreciated...
In class we have looked at the design of an equality compare module. For this problem you should design a magnitude compare module for 4 bit unsigned binary numbers. The module inputs are A[3..0] and B[3..0]. The two outputs are G and L, such that G is true iff A is greater than B; L is true iff A is less than B. (Thus if A == B, G and L are both false, and GL = 11 should never occur).
- Design and implement this compare module iteratively in space, by designing a cell with inputs Ai and Bi and gi and li, and outputs Gi and Li. How long will this comparison take?
- Design and implement the compare module using a hierarchical approach. How long will this comparison take?
- Using one instance of the cell from 1), design and implement the 4-bit compare module using an iteration in time technique. Show your complete design, including the data path and controller for this approach.
Where e means all stages to the right are equal, & E means this stage and all stages to the right are equal.
I figure the magnitude compare module must look similar with two compare blocks as above, but instead with four bit inputs.
My first block would have inputs A3, A2, A1, A0 and my second block would have inputs B3, B2, B1, B0.
The spec says there are two outputs G & L. So would each block contain both outputs or each block would contains one of each?
i.e. block one: G & L; block two: G & L
or block one: G; block two: L
???
I really am lost. I don't know exactly how a magnitude compare module differs from an equality compare module.
I first began this problem with a truth table.
After this, I got stuck and now I have no idea where to go from here.
Could someone please guide me with steps on what to do and how to implement this problem?
Any help will be greatly appreciated...
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