Hi all,

I have a very simple LVDS setup. My impedances are also not matched yet.
I just wanted to see and compare my inputs vs outputs. What is strange is that there is no DC component at the output. The reference is set to 0.

 

The reference is set to 0.

If it's set to 0, why do you expect a DC output component?

 

Not sure I understood your point. At my input,
V_common = 1/2 (v_1+V_2)= 1/2 (1.75+0.25)=1 V.


Thus, i was expecting that output will have the same common voltage though output voltage values might differ due to impedance mismatch. But my DC component is 0

 

Hi amahd1,
Please post your LTSpice asc file.
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I see no definition of V2 or V3. Perhaps the simulator sees them as open circuits??
AND, I am not familiar with whatever the symbol "T1" is representing, although the text implies it might be a transmission line of some sort.

 

hi am1,
This is your circuit, as you can see there is no Vout, on va, vb.
Where did you see the asc plot images ?

Check this link
https://iexploresiliconvalley.com/2019/08/27/ltspice-lesson-3-transmission-lines-part-1/
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BTW: if a Vource has a voltage applied to one of its pins from another source, then setting a voltage for that source is not required, the Vsource is just a short circuit.

 

OK, that is strange. Here is my model attached.

My results are also similar to what i was getting.

 

hi am1,
The reason is marked in this image , why did you make the parameters of the V sourcse invisible????
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I am really sorry. This info sometimes overwrites the resistor values on the screen so I hid it. Lesson for the next time

 

hi am1.
Don't worry, we have all been there.

What DC offset did you expect to see on the plots?
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I think I have figured it out the issue.
My idea was that if my LVDS has Vcommon of 1 V which is also my Dc bias, I would get it on the output too.

But in LTSPICE, the TL model is only for one mode communication and I would need at least one more TL . there is an example in "help" but its is hard to follow for me, and I was wondering how to get the VCommon also on output.

 

hi am1,
This sim shows that the Common voltage V=0v or if V=1v, it is added to the positive and negative amplitude of the pulses, so at the Vout they always cancel out, no DC offset.
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hi am1,
Could you post a sketch of the output waveform you require, so that I can check my circuits?
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Something like this where blue and green are inputs , red and yellow lines are at the output.
So inputs and outputs are at 1 V DC offset,

 

 

hi am1.
Look at this test sim, the tline component is removing the DC component on the input signal.
I have used simple +1V DC signal on one of the inputs, which is removed by the tline.

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