LTspice, Dflop


Joined Jan 10, 2012
I suggest that you post your asc file and someone in here can run it and find out what's wrong. I also suggest you post electronic related questions in one of the technical forums, say General Electronics Chat. The 'off topic' forum is not for technical questions.


Joined Mar 31, 2012
I'd also recommend posting a schematic image (PNG generally works best) so that people can view the circuit you are trying to work with. Many people won't have the simulator you are using or won't download files, but can identify your problem with just a quick glance at the circuit.


Joined Mar 31, 2012
Could you please post an image of the schematic? I'm one of those people that, as a rule, will not download binaries.


Joined Mar 31, 2012
Next is to post a shot of your simulation results (I should have asked for that before -- sorry).

I think your shift register is probably doing exactly what you are telling it to do -- but it depends on the initial conditions that the simulator arrives at.

It looks like you are trying to make a power-on set by having the PRE inputs of all the FF be HI for a short amount of time after the circuit starts and then help LO after that. But the time constant of that circuit is 1 ms and your clock has a period of less than half that.

Let's say that the power-on circuit does what you want. What does it do? It SETS all three FF to HI. You then start shifting a HI in from the left. What will each FF do? It will stay HI.

But I suspect your power-on circuit isn't playing any role because you are driving it with a DC source, meaning that the simulator is going to try to determine the voltage on the capacitor in that circuit when driven by a DC source at time t=0, which would have it fully charged and the PRE inputs pulled LO.

Try using a PWL source for the PRE input and a different one for the D input. That way you can have all of the input waveforms doing exactly what you want them to do.


Joined Mar 14, 2008
One error is that the power-on reset circuit should go to the CLR (to set all the Q outputs low) not the PRE inputs.

But even with that correction the circuit does not work properly.
All the FF Q outputs go high at the first clock pulse.
After some experimentation I determined that the problem is that the ideal FF model they use apparently has no propagation delays built-in as a normal model would. Thus when the first flip-flop output goes high it instantly propagates through the whole chain on the rise of the clock.
I got it to work properly by putting a small (10ns) RC delay at the D-inputs to the 2nd and 3rd FF's as shown below.

I also simulated it with a CD4013 D-FF model I have and it that works too (without the added delay circuitry).
Suggest you download the CD4000 library from the Yahoo LTspice user's group if you want to do any more digital simulation.

Shift Reg.PNG