Hi. I'm sim'ing an IR2110 driving a half-H-bridge for a boost converter (24V-->50V). The sim works for a few pulses and then the high-side FET stops turning on, but conduction continues thru the body diode. I've established that it's the IR2110 that is failing, although the low-side continues to work fine. Can anyone confirm that device failure is modeled in LTSpice, and if so, how can I tell which param breach caused the failure? I've been browsing the datasheet and checking the peak V and I along the high-side and they're all well within acceptable ranges. dVs/dt also seems acceptable at ~1V/ns. I managed to prevent failure by reducing the duty cycle of the high-side only, but I was never at risk of simultaneous low-side high-side conduction.

The model I used for IR2110 is here. It's a pspice model but I just dropped it into my LTspice schematic and it worked as expected (briefly): http://www.irf.com/product-info/models/sim/

 

Hi.
You can give us your files (asc, sym, lib or sub)?

 

Ok I'll have to do this tonight. I'm at work at the mo.

 

Can anyone confirm that device failure is modeled in LTSpice

Can't speak for all models, but I've not come across it with any models I've used. Most are quite happy to be outrageously over-driven without complaint; unlike real-world components.

 

Can't speak for all models, but I've not come across it with any models I've used. Most are quite happy to be outrageously over-driven without complaint; unlike real-world components.

Yeah, that's kinda what I expected. Or at least if something did enter failure mode it'd be made obvious. Perhaps I put the subckt in some weird internal latchdown mode. I'll post the helpful files in a couple of hours anyway.

 

Hi.
You can give us your files (asc, sym, lib or sub)?

.asc attached, along with 2 model/subckt definitions. This is what I get when plotting the V across the low and high-side FET gates. The high-side gives up after 5 pulses. Any insight would be much appreciated

PS. Note that I added 3 extra "COM" pin in the IR2110 definition to make the pin count up to 14. I got an error that the number of pins of the subckt and the device don't match so this was my workaround

 

PULSE(0 5 1m 0u 0u 12u 30u 10) ==> PULSE(0 5 1m 40n 40n 12u 30u) and
PULSE(0 5 1.014m 0u 0u 14u 30u 10) ==> PULSE(0 5 1.014m 40n 40n 14u 30u)

 

PULSE(0 5 1m 0u 0u 12u 30u 10) ==> PULSE(0 5 1m 40n 40n 12u 30u) and
PULSE(0 5 1.014m 0u 0u 14u 30u 10) ==> PULSE(0 5 1.014m 40n 40n 14u 30u)

Ok, I've tried adding the 40n rise/fall times but it still fails
PS. just tried 100ns and it only managed 2 pulses before giving up
PPS. and I tried adding 100ohm parasitic resistance to the pulse gens and this caused the IR2101 to fail in ON mode ie. high-side gate stays on

 

40n ==> 10n.
On my home computer all said good!
Your gate resistors LTspice shorted. Try Alternate method. At my work computer there are glitches. And some scheme it considers is not right! I will try your circuit tomorrow at work.

 

I never managed to get IR's 'official' IR2110 model to work properly, so finished up building my own model. I can post it if you're interested. The model runs fast, albeit with timings approximated.

 

40n ==> 10n.
On my home computer all said good!
Your gate resistors LTspice shorted. Try Alternate method. At my work computer there are glitches. And some scheme it considers is not right! I will try your circuit tomorrow at work.

Yes I shorted the gate resistors. I put them in as 5ohm and it did seem to stop the failure (within 10 pulses anyway), but it badly affected the transitions (as expected).

Alec_t, yes if you have a better model please send it!

 

Either way it seems that the conclusion will be modeling error ie. the real-world circuit would work.

 

My computer at work turned out to be worse than yours. But I coped with the problem that occurs. I was a little improved model of the chip. See changes at the end of the file.
See BB.zip

 

Ok, you commented out a couple of lines that branch depending on operating conditions. I'm assuming these may be causing the latching observed. Thanks for looking into this.

I see other people simulating whole circuits in LTspice. I tend to only simulate isolated blocks to test elements of the design that I have doubts about eg. here I was trying to get a rough gauge for the efficiency I can expect, which I've concluded can be >95% and the cap's ESR will probably be the bottleneck.

 

Here are the model files. Enjoy.

 

I do not just comment out couple of lines. In place of them I added a controlled current generator. In this way, (the voltage generator replacement and rezisor on current generator and a parallel resistor) I decided a lot of problems with simulation.

 

I see other people simulating whole circuits in LTspice. I tend to only simulate isolated blocks

Like you, I generally simulate only a block. The advantage is that the sim runs a lot faster. I would normally only sim a whole circuit if (a) it had few components or (b) there were unavoidable important interactions between blocks which couldn't simply be replaced by a behavioural current/voltage source.

 

I do not just comment out couple of lines. In place of them I added a controlled current generator. In this way, (the voltage generator replacement and rezisor on current generator and a parallel resistor) I decided a lot of problems with simulation.

Ah yes sorry. I'll plug these subs into my sim tonight. Thx for you help guys