I have a simulation in LT Spice that I'm having trouble with.

I understand that switching components are hard to simulate, but I run into convergence issues at 20 μs and I can't figure out how to fix them. Until then, the circuit runs as I expect it to. I've tried several ".OPTIONS" commands in regards to my sim tolerances, and tried using the alternate solver. I still end up with the same error messages. Is the issue with my custom components? I've attached the components and their .lib files to this post.

 

How can the kicad files help with sim problems?
Post your .asc LTspice file.
And please don't zip it.

 

The error messages suggest you are using a monolithic MOSFET (intended for fabrication on a wafer) rather than a discrete MOSFET, or alternatively a sub-circuit.

 

The circuit needs fixing first. A voltage source (V3) feeds through L1 the actual output node. The output is taken where the supply voltage for the MOSFETs should be. Load R1 in parallel with 15uF? 15pF (C2, C4) as bypass cap? Bootstrap cap (C1) to small?

 

How can the kicad files help with sim problems?
Post your .asc LTspice file.
And please don't zip it.

I should have mentioned that this included the .asc file. I also didn't even think about how sketchy it was to ask people to download a random .zip file. The Kicad files are used to make the custom components in LT Spice and may be useful in understanding how or why the simulation doesn't work.

 

The error messages suggest you are using a monolithic MOSFET (intended for fabrication on a wafer) rather than a discrete MOSFET, or alternatively a sub-circuit.

After doing some research, I believe this is just an artifact of LT Spice's age and unfamiliarity with modern transistor sizes and the error message about length is harmless. Or at least, that's what I've read online. This same file worked fine in KiCad.

 

What is changing at 20.15 µs? As best I can tell, that appears to be the moment that your V2 source is just finishing it's fall and transitioning to it's LO state. That's where you want to focus your investigations.

Look closely at the voltages and currents associated with nodes that are changing there. You might also see if you can tease some more information from the simulator, such as which nodes are having convergence issues.

Simplify your schematic as much as possible and see if the problem goes away, and then add in components until it appears. That will help you zero in on the problem.

 

See

 

What is changing at 20.15 µs? As best I can tell, that appears to be the moment that your V2 source is just finishing it's fall and transitioning to it's LO state. That's where you want to focus your investigations.

Look closely at the voltages and currents associated with nodes that are changing there. You might also see if you can tease some more information from the simulator, such as which nodes are having convergence issues.

Simplify your schematic as much as possible and see if the problem goes away, and then add in components until it appears. That will help you zero in on the problem.

I've actually just returned from noticing this and looking into it. A few notes:

1. My simulation works fine at a switching period of 75 μs. At least, it finishes uninterrupted. Any lower and it runs into the same convergence issues.
2. I'm sure the problem isn't my MOSFETs, as I tested the model separately and it works fine.

This leads me to believe that my problem can be fixed by loosening LT Spice tolerances and changing the simulation settings to account for the frequency. Any suggestions on this would be appreciated.

See
View attachment 360185


View attachment 360186

I'm unfamiliar with this program, and I sadly cannot use it. LT Spice is the only valid program for this simulation. Thank you for trying, though.

 

This is the Qspice program. I have shown that when switching on, the output voltage is released. In the second diagram, I adjust the borehole over time. This made it possible to avoid an emergency situation.
I used LTspice and created an extensive library of models for it. Now I'm switching to Qspice. This is a more advanced program and it's easy to add new models.

 

I've actually just returned from noticing this and looking into it. A few notes:

1. My simulation works fine at a switching period of 75 μs. At least, it finishes uninterrupted. Any lower and it runs into the same convergence issues.
2. I'm sure the problem isn't my MOSFETs, as I tested the model separately and it works fine.

This leads me to believe that my problem can be fixed by loosening LT Spice tolerances and changing the simulation settings to account for the frequency. Any suggestions on this would be appreciated.

My gut feel (and that's all it is) is that it is likely related to trying to switch of the current in that inductor too quickly.

 

hi CM,
This is a sim of the circuit without the MOSFET's
The upper MOSFET Gate to Source is just on the Vg threshold, not fully being turned On.
E

 

hi CM,
This is what the sim shows when using an approximation of the d/s example circuit.
The MOSFET's and Driver works OK, but it is very voltage sensitive at the lower supply voltages.
E

 

The upper diagram shows the pulse durations of the PWM signal. Such durations, smoothly changing so that there is no large excess of output voltage and choke currents.

 

hi CM,
This is a sim of the circuit without the MOSFET's
The upper MOSFET Gate to Source is just on the Vg threshold, not fully being turned On.
E

View attachment 360190View attachment 360191

That is MOSFET VG threshold issue is not the case in my simulation

hi CM,
This is what the sim shows when using an approximation of the d/s example circuit.
The MOSFET's and Driver works OK, but it is very voltage sensitive at the lower supply voltages.
E
View attachment 360202View attachment 360203

I was able to get similar results in this configuration, but I need to simulate this as a boost converter and the datasheet uses a buck converter layout. What's even worse, this layout sometimes finishes the simulation, sometimes gets stuck in convergence issues.