Hello All,
Could you please help me on below query ?
LTspice file is attached.
The objective of this circuit is to give some delay to turn ON the Q1.
1. What is the JFET biasing on below circuit (i do not understand) ?
Since jfet Gate is connected to D1, R1 & C1 junction. What is reason behind that ?
2. How transistor Q1 is getting turned ON ?
3. At startup for 51.8us why Q1 is getting turned ON ?
Could you please help me on below query ?
LTspice file is attached.
The objective of this circuit is to give some delay to turn ON the Q1.
1. What is the JFET biasing on below circuit (i do not understand) ?
Since jfet Gate is connected to D1, R1 & C1 junction. What is reason behind that ?
2. How transistor Q1 is getting turned ON ?
3. At startup for 51.8us why Q1 is getting turned ON ?
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