LT Simulation help needed

Thread Starter

mishra87

Joined Jan 17, 2016
939
Hello All,

Could you please help me on below query ?
LTspice file is attached.

The objective of this circuit is to give some delay to turn ON the Q1.

1. What is the JFET biasing on below circuit (i do not understand) ?
Since jfet Gate is connected to D1, R1 & C1 junction. What is reason behind that ?

2. How transistor Q1 is getting turned ON ?

3. At startup for 51.8us why Q1 is getting turned ON ?

1632745485828.png
 

Attachments

ericgibbs

Joined Jan 29, 2010
13,881
hi
The objective of this circuit is to give some delay to turn ON the Q1.

1. What is the JFET biasing on below circuit (i do not understand) ?
Its a Constant current source, that charges up the 100n cap with a linear ramp.

2. How transistor Q1 is getting turned ON ?
When the voltage on the 100n exceeds the 12V Zener voltage the transistor is turned ON

3. At startup for 51.8us why Q1 is getting turned ON ?
I don't see a turn ON, unless you mean that 'blip'

E
EG 843.png
 

Thread Starter

mishra87

Joined Jan 17, 2016
939
Thanks for your comments.

Yes i was talking about a start blip. Why this is happening ?
Basically this is turning ON the Q1 for shorter time and that is problem for me. I do not want a blip.
This is unusual behavior of transistor and that will false trigger the load connected at Q1.

Additional point if you notice that there is always 0.5V at Q1 base before reaching to 0.7V, i do not understand why ?

Thanks in advance !

Regards,
M
 

dcbingaman

Joined Jun 30, 2021
476
That is just base to emitter capacitance. There is a small leakage current from base to emitter. By adding a bias resistor you can eliminate that 0.5V as shown attached.
 

Attachments

crutschow

Joined Mar 14, 2008
27,956
I see no reason for the JFET constant current source, unless you need the delay to be relatively independent of the supply voltage.
For a fixed supply voltage, you can just remove J1 and change R1 to a larger value that gives the delay you want.
 

dcbingaman

Joined Jun 30, 2021
476
D1 along with Q1 B-E junction have a capacitance that must charge at initial turn on. That is the 'blip' you are observing when the circuit first turns on.
 

dcbingaman

Joined Jun 30, 2021
476
I see no reason for the JFET constant current source, unless you need the delay to be relatively independent of the supply voltage.
For a fixed supply voltage, you can just remove J1 and change R1 to a larger value that gives the delay you want.
It is a nice example though of creating a constant current source using a JFET.
 

ericgibbs

Joined Jan 29, 2010
13,881
hi,
I always to try to use the same circuit the TS has posted, unless he asks for a design modification.
They are usually interested in how their circuit performs, not my version of it.
E


Update:
Look at these two sims, with and without R5
EG 847.png
 
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Thread Starter

mishra87

Joined Jan 17, 2016
939
I see no reason for the JFET constant current source, unless you need the delay to be relatively independent of the supply voltage.
For a fixed supply voltage, you can just remove J1 and change R1 to a larger value that gives the delay you want.
Hi,

Your assumption is true but i want to avoid power supply variation .

Thanks !
 

Thread Starter

mishra87

Joined Jan 17, 2016
939
Thank you all for your comments .
That really made me to understand about circuit working.

I still looking for JFET constant current working. Over the internet i found that Gate of the JFET is connected to GND that (Vgs=0V) to turn ON the JFET in saturation mode.
But in this circuit the gate of the JFET is connected to the VD1+VBE. Additional drop across R1.

Could any one explain me how JFET works as constant current for this circuit ?

Thanks,
 

ericgibbs

Joined Jan 29, 2010
13,881
hi m,
It is a Deletion mode jFet,
Which means it requires the Gate to be negative with respect to the Source to reduce the Drain to Source current rate, about -8v will turn it completely Off.

The resistor in the Source generates a positive voltage on the Source pin,due to the On current flowing from Drain to Source, which makes the Gate a negative voltage wrt the Source.

The value of the Source resistor effectively sets the current level flowing from Drain to Source.
Experiment by changing the Source resistor value and note the Vramp cap charge rate.

OK
E

Note: the Vs and Vs2 voltages

Changed the X axis for a better plot.

EG 849.png
 
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Thread Starter

mishra87

Joined Jan 17, 2016
939
Hi,

Thanks for your reply !
I just wanted to understand theoretically how this works.
With LT spice measurement i see that
Vs = 15V
Vg = 12.6V
Vgs = Vg-Vs = 12.6-15V = -2.4V with this Vgs JFET is working in linear region not in saturation region. Am i correct ?
JFET to be worked saturation region Vgs = 0V

Unless and until capacitor charges upto VD1+Vbe the Gate voltage of JFET will ramp up from 0V.
1632755201716.png
1632755220231.png
 

ericgibbs

Joined Jan 29, 2010
13,881
hi,
Yes, it is in its linear region -Vgs versus Ids.
If -Vgs was say -8v , then the jFET will be OFF, not conducting.

For Vgs=0v saturated. Ids max.

These jFET's are often used in Audio gain and Oscillator circuits

The complementary jFET is the 2N3820 P type.

E
 
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crutschow

Joined Mar 14, 2008
27,956
One possible disadvantage of that circuit is that there can be a significant difference in the constant-current from unit to unit, due to the large variation in the JFET's Vgs control voltage (see below for the 2N3819 values, which shows a 15:1 difference).
This would require adjusting the source-resistor value to get the desired current.

1632756628010.png
 
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