I neglected to mention that I'm running the CLK at 8MHz. So far, every frequency I've tested (<= 8MHz) has worked flawlessly.Part of the effect is to introduce a low-pass filter formed by the IC's input capacitance and the resistor. That's often a bad thing to do, but the chip has hysteresis on those inputs so it will tolerate slow transitions with no problem and the clock rate isn't very high.
That's what I'm seeing. The resistors filter glitches from the MAX chip to the bus and from the bus to the MAX chip. Its rather amazing the difference it makes.The filter will work from "both sides" of the resistor - if there is noise on the clock it will filter some of that, if the the IC ground bounces (as it will), it will defend the clock input from some of that.
Also, the last module is now unterminated. At one time I had pullup and pulldown resistors on the signals and caps on the power, but all of that is gone now. The only change in capacitance is that I moved the 10uF and 0.1uF bypass caps closer to the chip. That alone didn't fix anything, but I went ahead and modded all the boards anyway.
Thanks for all your help (and everyone else's too). I know I'm not the only one with this problem because there are threads all over complaining about the problem, but nobody had a real solution - until now.

