Hi all,
Can anyone help me with the below exercise ?
I have to "Build a circuit that has two 8-bit two’s complement numbers U and
W as its inputs and a single 1-bit output R, which is 1 when W − U is
negative and 0 otherwise." In logisim
Thank you

 

hi VN,
Welcome to AAC,
As this is homework please post your best attempt and then we can help you.
E

 

Hi,
This is what I have done so far 8-bit incrementer subcircuit, 8-bit subcircuit adder, 8 subcircuit bit mux , the problem is if W-U is negative output should be 1 or otherwise 0 I cant think of anything elce to solve this please see attacher logisim file

 

For convenience, the aforementioned adder circuit:

 

Hi,
This is what I have done so far 8-bit incrementer subcircuit, 8-bit subcircuit adder, 8 subcircuit bit mux , the problem is if W-U is negative output should be 1 or otherwise 0 I cant think of anything elce to solve this please see attacher logisim file

How can you subtract one two's complement number from another number using an adder?

 

Hi,
This is what I have done so far 8-bit incrementer subcircuit, 8-bit subcircuit adder, 8 subcircuit bit mux , the problem is if W-U is negative output should be 1 or otherwise 0 I cant think of anything elce to solve this please see attacher logisim file

Did you solve it ??