Hi all,

From the attached schematic diagram, how can I do a NAND gates minimization?

Thanks in advance.

 

Looks like you cut a couple minterms from the bottom there

No worries...

The easiest way would probably utilize DeMorgan's theorem in order to make the minterms into all NAND implimentations.

You could also attempt to redraw the circuit with NANDs and try to reduce that way.


Now, before you ask more questions, post some of your work.

 

Hi tshuck,

I managed to do the NAND gate minimization, but is there a way to simplify the circuit (the one attached) ??

(by the way, the photo shows a part of the circuit)

Thanks.

 

Any help please? I tried using boolean algebra but I did not manage to minimize it while leaving all gates as NANDs.

 

If you did the work, post it....

Also, your transformation to an all NAND implementation is wrong.

See here
specifically, this:

 

You should start by getting some minimal form of the input, and then translate the logic functions to gates. Also check if your requirement asks specifically for 2-input nand gates, that complicates things a little more.

 

Any help please? I tried using boolean algebra but I did not manage to minimize it while leaving all gates as NANDs.

Hint: You have to be comfortable with DeMorgan's Theorem to work the Boolean magic....