Hi all,
From the attached schematic diagram, how can I do a NAND gates minimization?
Thanks in advance.
From the attached schematic diagram, how can I do a NAND gates minimization?
Thanks in advance.
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Hint: You have to be comfortable with DeMorgan's Theorem to work the Boolean magic....Any help please? I tried using boolean algebra but I did not manage to minimize it while leaving all gates as NANDs.