Hi.
I am having some trouble trying to make an ultrassonic signal.
I have 2 crystal oscillator square waves (very stable clocks), and I want to make a gated square wave pulse train with them.
Feeding both square waves to the 74LS132N chip, gives me the desired output.
The only problem is that, the output signal gets too dirt, jittering (the square waves moves back and forth) and my oscilloscope can`t even trigger it, and I can`t even drive my device with this signal.

I`ve already decoupled the chip with a electrolytic cap and a ceramic one, and even fed the chip thru a resistor to make a RC decoupler.
I`ve already pulled all the unused inputs to +Vcc via a 1k Ohm resistor.

Am I missing something here? Or is this a common characteristic of the 74 family? Is there a better way to do it?

Thanks.

 

It sounds like everything is working the way I would expect. The output will be low whenever both clock inputs are high and low otherwise. Even if the clock inputs are phase locked and synchronized, small variations in duty cycle will provide ample opportunity for outputs that get "to dirt" as you put it. You need to rectify your expectations. Trust me it is not the fault of the logic gate.

 

But, is there a better way for doing this gated signal without messing it? I need a very stable and precise oscillator (thats why I`m generating these clocks with a crystal oscillator), the equipment I`m driving has a high Q (and consequently a narrow bandwidth) can`t have this jitter in it...
Thanks again...

 

For a gated oscillator, use something such as 74LS124.

Lots to choose from:

74LS124

74LS324
74LS325
74LS326
74LS327

74LS624
74LS625
74LS626
74LS627
74LS628
74LS629

 

But, is there a better way for doing this gated signal without messing it? I need a very stable and precise oscillator (thats why I`m generating these clocks with a crystal oscillator), the equipment I`m driving has a high Q (and consequently a narrow bandwidth) can`t have this jitter in it...
Thanks again...

I don't see how you get a stable and precise oscillator by applying two clocks to a gate. It sounds like what you need is a TCXO, a temperature compensated oscillator. Producing a gated oscillator should be done with a state machine to make sure there are no partial cycles. It is true that a VCO should be an improvement, but it may or may not give you the degree of stability you require.

http://www.newark.com/c/crystals-os...MIvpPRjKia1QIVz2F-Ch121AzKEAAYASAAEgJeHvD_BwE

 

For a gated oscillator, use something such as 74LS124.

Lots to choose from:

74LS124

74LS324
74LS325
74LS326
74LS327

74LS624
74LS625
74LS626
74LS627
74LS628
74LS629

Thanks, I`ll look into it.

I don't see how you get a stable and precise oscillator by applying two clocks to a gate. It sounds like what you need is a TCXO, a temperature compensated oscillator. Producing a gated oscillator should be done with a state machine to make sure there are no partial cycles. It is true that a VCO should be an improvement, but it may or may not give you the degree of stability you require.

http://www.newark.com/c/crystals-os...MIvpPRjKia1QIVz2F-Ch121AzKEAAYASAAEgJeHvD_BwE

Thanks too. I`ll look into the link.

A state machine can be done using some 4017 I.C`s dont it?

 

Yes. That is one variation - count down the higher of the two frequencies to make the gating signal.

 

There are many possible ways to do a state machine, but using programmable logic or FPGA gives you access to synthesis tools that will save you boatloads of time.

 

Yes. That is one variation - count down the higher of the two frequencies to make the gating signal.

Thanks for the tip.

But, doing this, won`t I have to use the same AND gate to make the gated signal? If I count down the higher frequency, I`ll have a slow frequency for the gate, and the original high frequency on distinct outputs...
I did a test a long time ago, but using a 7490 divider. I got the clock and the output from the 7490 with the scaled clock and fed them both to the AND gate again, but the results were the same, even with both signals from the same clock...

Or there is another way to make the gate?

 

There are many ways to gate a signal. The problem you reported was not related to the type of gate, it was related to the two signals being asynchronous. If you are dividing the higher frequency signal to obtain the gating signal you should not see the problem you reported, at at least that we think you reported.

 

There are many ways to gate a signal. The problem you reported was not related to the type of gate, it was related to the two signals being asynchronous. If you are dividing the higher frequency signal to obtain the gating signal you should not see the problem you reported, at at least that we think you reported.

Sorry if I didnt make myself clear. The original problem was, I got 2 signals, from the same crystal clock, I`m just dividing the clock and outputting a different frequency in each output pin, but the 84MHz crystal is the same for both and, when I try to make the gated signal, with an AND gate, the gated signal get noise and jittering.

I did make a gated signal with a divider in the past, (like you told me), but I had to put both again in the chip, messing my signal in the same way.

As I see, I need to gate a signal without the AND logic gate, which is messing it badly with noise and jitter. And I don`t know any other way of doing without it...

Thanks again.

 

Hello,

What about clock gating:
http://vlsi.pro/integrated-clock-gating-cell/

Bertus