First, regarding resolution, you are trying to resolve about 1 nV from an FSO of 20 mV at 100 Hz. You think this is possible? If so, please support your claim.

Regarding the posted circuit, you ask "Will it minimize drift?". The answer is, "With respect to what?" It gives you drift specs in the text. Are these figures better than, or worse than, what you have achieved by other means?

What do you mean by "minimize"? Do you want the absolute best performance regardless of price? Then this circuit probably does not represent a minimum.

A better approach is to define what you (or your customers) need, and then find the best overall solution to fill that need. And then build and test, test, test, to ensure you've achieved those specs.

And don't fall into the trap of "I've got a 24 bit converter, therefore I'm gonna get 24 bits of useful data out -- and fast."

 

First, regarding resolution, you are trying to resolve about 1 nV from an FSO of 20 mV at 100 Hz. You think this is possible? If so, please support your claim.

Regarding the posted circuit, you ask "Will it minimize drift?". The answer is, "With respect to what?" It gives you drift specs in the text. Are these figures better than, or worse than, what you have achieved by other means?

What do you mean by "minimize"? Do you want the absolute best performance regardless of price? Then this circuit probably does not represent a minimum.

A better approach is to define what you (or your customers) need, and then find the best overall solution to fill that need. And then build and test, test, test, to ensure you've achieved those specs.

And don't fall into the trap of "I've got a 24 bit converter, therefore I'm gonna get 24 bits of useful data out -- and fast."

Thanks Joey... for starts, I'm not making any claims, I'm only trying to fully understand what ADC in the field of load cells is all about. Sorry if it sounded like I was trying to make a claim, please remember that English is not my first language.
As I said before, I've been working with them for a long time now, but my area of expertise is digital electronics. Analog electronics is my one big weakness here. What I've been doing is copying and pasting circuitry from many sources to try to accomplish what I want, but maybe, as you've just implied, I've been trying to get unrealistic performance out of those systems.
In my digital mind, 16 bits is equal to 65,536 divisions, and 24 bits is 2^24 divisions. Now I've worked with 16 bit ADC chips before, and I can get full scale output from them by simply placing a trimpot as a voltage divider at its input and play with it, but it seems that a 24 bit ADC is an entirely different animal for some reason that I yet fail to grasp.
For one thing, I have to admit that I do not fully understand the concepts of single ended, pseudo-differential, and fully differential inputs. What are their differences and benefits?

Anyway, to answer your question, this is what I want: I want to be able to get full 16-bit readings (with as low offset drift as possible) from a load cell with a maximum capacity of 1 Kg. That is, I want to see if I can make readings in 0.015g increments out of that cell. But I have to admit that increments of 0.15g would be pretty fantastic too.

Now, I'm going to try to do my homework here, and see what that implies for a cell with the characteristics that I mentioned in post #19

Hysteresis = 0.05% of R.O.
Nonrepeatability = 0.05% of R.O.
I'm not concerned about non-linearity, since that is something that can be calibrated through multiple point interpolation (but I'm not sure if I'm mistaken there).
​

If I only consider Hysteresis, for instance, that means that for a 1Kg load cell its hysteresis will be 0.5g, and it's nonrepeatability will also be 0.5g. So it's probably very unrealistic of me to demand increments of 0.15g when reading that cell, regardless of how great and perfect the ADC that I choose to use is. Right?

 

Thanks Joey... for starts, I'm not making any claims, I'm only trying to fully understand what ADC in the field of load cells is all about. Sorry if it sounded like I was trying to make a claim, please remember that English is not my first language.

I am just trying to help you crystallize your thinking. Yes, you made (inadvertently) a claim: a 24 bit A/D converter should provide a 24 bit (ENOB) result. Stated another way, you suggested that you should be able to resolve 1 nV out of 20 mV (at 100 Hz). What I want you to think: is this possible? If so, why? If not, why not?

As I said before, I've been working with them for a long time now, but my area of expertise is digital electronics. Analog electronics is my one big weakness here.

Very common. That is why I told you to stop thinking digital, and think analog first. Look at the RMS noise and resolution tables in the datasheet on pages 15 thru 18. These figures represent input referred noise (i.e. noise sources in series with the output of your load cell). From the tables, can you tell me what your best possible resolution (and at what data rate) you can achieve with this chip?

What I've been doing is copying and pasting circuitry from many sources to try to accomplish what I want, but maybe, as you've just implied, I've been trying to get unrealistic performance out of those systems.

Not unrealistic in the sense of asking for something that's impossible. You just haven't defined your requirements (or desires) in quantifiable analytic terms. Until you do that, you're throwing darts at a dart board.

In my digital mind, 16 bits is equal to 65,536 divisions, and 24 bits is 2^24 divisions.

Nope. In the scale world, d -- number of divisions -- is the number of discrete measurements that are displayed to the user. So, a 5kg scale with 5000 divisions will display in 1g increments. Does this mean they uses an A/D converter with 1 in 5000 resolution? Absolutely not. Generally, the load cell is sampled at a much higher resolution than actually displayed. In this way, "games" can be played in software to achieve the rock-solid display required for an NTEP or OIML commercial certification.

Now I've worked with 16 bit ADC chips before, and I can get full scale output from them by simply placing a trimpot as a voltage divider at its input and play with it, but it seems that a 24 bit ADC is an entirely different animal for some reason that I yet fail to grasp.
For one thing, I have to admit that I do not fully understand the concepts of single ended, pseudo-differential, and fully differential inputs. What are their differences and benefits?

Single Ended: Input voltage is referred to ground -- no "common-mode" rejection.
Differential: Input voltage = (In+ - In-) -- good common-mode rejection. (What's so hard?)
Pseudo-differential: Same as differential, excepting that In- is usually referred either directly to ground, or via a low impedance. Common-mode rejection not nearly as good as true, fully differential inputs.

You cannot use a single-ended input with a load cell -- at least not without first converting the differential load cell output to a single-ended signal with, say, an instrumentation amp. If you tried, you'd be attempting to resolve nV of signal amongst volts of noise.

Pseudo-differential is not so good for load cell either (as both +/- change with weight), and common-mode rejection will likely not be high enough to meet your performance goals. You'll want to stick with either fully differential A/D, or a single-ended A/D with an instrumentation amp on the front end. Note the latter requires a bipolar supply (to do it right!), and you now have to concern yourself with the drift and noise performance of the amp and associated components.

Anyway, to answer your question, this is what I want: I want to be able to get full 16-bit readings (with as low offset drift as possible) from a load cell with a maximum capacity of 1 Kg. That is, I want to see if I can make readings in 0.015g increments out of that cell. But I have to admit that increments of 0.15g would be pretty fantastic too.

Now, I'm going to try to do my homework here, and see what that implies for a cell with the characteristics that I mentioned in post #19

Hysteresis = 0.05% of R.O.
Nonrepeatability = 0.05% of R.O.
I'm not concerned about non-linearity, since that is something that can be calibrated through multiple point interpolation (but I'm not sure if I'm mistaken there).
​

If I only consider Hysteresis, for instance, that means that for a 1Kg load cell its hysteresis will be 0.5g, and it's nonrepeatability will also be 0.5g. So it's probably very unrealistic of me to demand increments of 0.15g when reading that cell, regardless of how great and perfect the ADC that I choose to use is. Right?

Excellent! You've demonstrated to yourself that you will not exceed 1/2 gram (likely, a bit more) of performance with this particular load cell. The cell quality is on the order of a 1000 to 2000 division load cell.

Let's go with 2000 division. This means that each division represents an analog change of 10uV. You want each division to be "solid" so, if we assume Gaussian noise with a crest factor if 6, our input-referred noise cannot exceed 1.666 uV RMS. Look at the noise tables referenced above, and find a combination of gain and data rate with an RMS noise less than 1.666 uV RMS. From this you can figure your offset/gain drift due to the A/D vs. temperature. I think you'll find the performance satisfactory with respect to the load cell you have chosen.

 

Very common. That is why I told you to stop thinking digital, and think analog first. Look at the RMS noise and resolution tables in the datasheet on pages 15 thru 18. These figures represent input referred noise (i.e. noise sources in series with the output of your load cell). From the tables, can you tell me what your best possible resolution (and at what data rate) you can achieve with this chip?

Not unrealistic in the sense of asking for something that's impossible. You just haven't defined your requirements (or desires) in quantifiable analytic terms. Until you do that, you're throwing darts at a dart board.
***
I think you'll find the performance satisfactory with respect to the load cell you have chosen.

Boy, you're one tough teacher... but this is good, it means that I've asked the right person.

Alright, I'm going to have to dust my hypothalamus here, and actually going to try to use my brains... I'll study the graphs you pointed out, and try to answer your questions and see if I'm moving forward with my understanding... then I'll get back to you with my hopefully not-so-off-the-mark thoughts on this.

In the meantime, thanks for taking the time to try to help me out here-

 

you suggested that you should be able to resolve 1 nV out of 20 mV (at 100 Hz). What I want you to think: is this possible? If so, why? If not, why not?

Ok, I've studied the AD7190 datasheet, and here are my thoughts:

According to table 12 in page 19, at 100 Hz output data rate, RMS noise at

RMS peak to peak
noise resolution
-------------------------------
Gain 1 1380 nV 20 bits
Gain 128 52 nV 18 bits

Now, just looking at the digital data, it is clear that I cannot get the whole 24 bits out of this chip due to its peak to peak resolution... but you wanted me to stop reasoning in digital terms and start thinking analog. From that perspective things look even worse.
The load cell's data on post #19 says that my load cell has a rated output of 2mV/V (nominal), that means that if I were to excite that cell with 10V, I'd get a maximum output of 20mV at maximum load, right?
So if I were to try to achive a perfect 24-bit resolution out of that range, I should be able to resolve 0.020V/2^24 = 0.0000000011920928955078125 V = 1.2nV, which is more or less what you said I claimed...
So! just looking at the tables you pointed out, the noise present at those scales is far greater than that signal. THAT is why it's impossible to resolve 1 nV out of those 20 mV under the conditions you specified.

The following reasoning is more or less a shot at the dartboard for me, but here it goes anyway:
Now, I ask myself, why is RMS noise smaller at a gain of 128 than at a gain of 1? Well, I think it's all a matter of proportions.

Maybe the key lies in what you said:

These figures represent input referred noise (i.e. noise sources in series with the output of your load cell)

So being input noise, this noise is actually multiplied at the internal amplifier's output, before it reaches the analog to digital converter:

input output
noise noise
----------------------------
Gain 1 1,380 nV 1,380 nV
Gain 128 52 nV 6,656 nV

So it seems that proportional noise is actually much greater when using a gain of 128, and that is why the effective peak-to-peak resolution is degraded to 18 bits (a difference of 2 bits, which is a fourfold multiplication of noise) at that setting.

Am I more or less on the mark here? Or, as Mr Wolfgang Pauli once said: "It is not only not right, it is not even wrong"

 

You've pretty much got it. You should remember that, typically, the front end PGA of a delta-sigma is digital, not analog. Therefore, noise contribution, especially 1/f, is usually negligible compared to an analog instrumentation preamp. In fact, the whole point of the converter is to remove the need for any analog front end whatsoever.

The only thing left for you is to recognize that the noise histogram has a very nice distribution of codes (with 'no missing codes'!) about a very well defined mean for any given input voltage. This means you can trade time for resolution. If you *really* want 1 nV resolution, all you need to do is average enough readings over time to accomplish this.

The S/N is improved by a factor of sqrt(N), when N is the number of samples accumulated.

 

You've pretty much got it. You should remember that, typically, the front end PGA of a delta-sigma is digital, not analog. Therefore, noise contribution, especially 1/f, is usually negligible compared to an analog instrumentation preamp. In fact, the whole point of the converter is to remove the need for any analog front end whatsoever.

The only thing left for you is to recognize that the noise histogram has a very nice distribution of codes (with 'no missing codes'!) about a very well defined mean for any given input voltage. This means you can trade time for resolution. If you *really* want 1 nV resolution, all you need to do is average enough readings over time to accomplish this.

The S/N is improved by a factor of sqrt(N), when N is the number of samples accumulated.

Thanks Joey, you have no idea of how much you've helped out me here... you've probably saved me countless headaches..
One last question. If you were to choose between two chips for a load cell application, which one would you choose?
The AD7190, or the AD7730?
Personally, I'm drawn towards the AD7730 because it has AC excitation capability and will probably improve offset drift dramatically. And although it seems to be able to deliver only up to 18 bit Peak-to-Peak Resolution, it does have a 24 bit ADC internally.
Even so, probably 18 bits on most load cells is more than enough, considering their average hysteresis.

 

I'm not gonna choose a part for you. Pick the specs that are important to you, and choose the best that you can afford.

BTW, I've never used either of these parts, though I am a big fan of the TI ADS1242/43.

 

I'm not gonna choose a part for you. Pick the specs that are important to you, and choose the best that you can afford.

BTW, I've never used either of these parts, though I am a big fan of the TI ADS1242/43.

Good looking part... with 8 input channels and all... and very affordable too! It's too bad it only comes in SMT package.
How do you avoid offset drift with this chip? Do you solder it by hand, or do you have an oven? Is it also extremely sensitive to soldering temp as my HI7190 is?

 

Good looking part... with 8 input channels and all... and very affordable too! It's too bad it only comes in SMT package.
How do you avoid offset drift with this chip? Do you solder it by hand, or do you have an oven? Is it also extremely sensitive to soldering temp as my HI7190 is?

I've probably hand-soldered a few dozen over the years with never a problem. And I've built 10s of thousands of boards with these chips via P&P and reflow, again with no problems.

 

Keep in mind that Analog Devices sells analog solutions (and are stunningly good at doing so) but lots of that stuff can be done with a cheap uC and some *ahem* good firmware.

I've been doing a little research regarding classifications of load cells, when I came across this image:



It seems that C6 is the highest quality available load cell in the market... but then what drew my attention was the extreme right of the image, which mentions "load cells using the principle of electromagnetic force compensation"....

Anyway, after some googleing, I was fascinated when found this page. Check the short video at the bottom explaining how it works.

It seems that this technology is the top-notch, non-plus-ultra thing in the field of weight measuring. It seems to be ultra-accurate, ultra-fast and even seems to have a very strong tolerance for external vibration and temperature changes.

Anyone here heard of this before? I wonder how easy or hard it would be to design and build a weight scale using the same principle.

 

I was once trying to repair a scale that was running on this principle where the ADC failed, but I still haven´t managed to make a replacement adc for it. I would guess the mechanical part will be the hardest to make in order to maintain good linearity across the whole range.

 

... but then what drew my attention was the extreme right of the image, which mentions "load cells using the principle of electromagnetic force compensation"....

Anyone here heard of this before?

Sure. It's the same principle behind electromagnetic force-balance accelerometers.

 

@joeyd999, I've been taking a closer look at the ADS1242/43 and it seems like a real beauty, especially when one considers its price and multiplexing capabilities.
Do you think it would be too complicated to use AC load cell excitation synced with that chip?
I already know how to excite the cell with AC, my question is how hard would it be to interface that sort of signal to the ADS1242.

 

Do you think it would be too complicated to use AC load cell excitation synced with that chip?
I already know how to excite the cell with AC, my question is how hard would it be to interface that sort of signal to the ADS1242.

Not hard at all.

 

Not hard at all.

Thank you Joey for succinctly teaching me about the subtle art of how to directly ask a question....

How would you suggest I did that?
Should I, for instance, make x number of readings, then invert polarity, make the same number of readings, and finally add the results and average them?
Or should I alternate polarity between single readings at a certain frequency and average the results in the end?
Or would you do it some other way?
And if some other way, how exactly?

 

Thank you Joey for succinctly teaching me about the subtle art of how to directly ask a question....

How would you suggest I did that?
Should I, for instance, make x number of readings, then invert polarity, make the same number of readings, and finally add the results and average them?
Or should I alternate polarity between single readings at a certain frequency and average the results in the end?
Or would you do it some other way?
And if some other way, how exactly?

I'd alternate each conversion.

From page 10 of the datasheet:

The ADS1242 and ADS1243 feature a single-cycle settling digital filter that provides valid data on the first conversion after a new channel selection. In order to minimize the settling error, synchronize MUX changes to the conversion beginning, which is indicated by the falling edge of DRDY. In other words, issuing a MUX change through the WREG command immediately after DRDY goes LOW minimizes the settling error. Increasing the time between the conversion beginning (DRDY goes LOW) and the MUX change command (tDELAY) results in a settling error in the conversion data, as shown in Figure 2.

Note that it is important to set the new MUX values immediately upon receipt of DRDY edge. Follow this rule, and you'll be fine.

BTW, you'll have to prove to me you get better performance with AC than DC.

 

I'd alternate each conversion.

From page 10 of the datasheet:



Note that it is important to set the new MUX values immediately upon receipt of DRDY edge. Follow this rule, and you'll be fine.

BTW, you'll have to prove to me you get better performance with AC than DC.

I cannot actually prove that I'd get better performance, since I have not built the thing. But I've been trying to fix (or at least improve) offset drift for years now. My fixation with this technique comes from at least three sources:

• Page 17 of the "49470200sscsect2 BRIDGE CIRCUITS.pdf" document
• Page 10 of the "AD630 Balanced Modulator~Demodulator.pdf" document
• Page 41 of the "AD7730_7730L.pdf" document, where it says: "AC excitation of the bridge addresses many of the concerns with thermocouple, offset and drift effects encountered in dc-excited applications."

The only thing that bothers me a little about the ASDS1242 is its low conversion rate when compared with other chips (30Hz tops)

 

The only thing that bothers me a little about the ASDS1242 is its low conversion rate when compared with other chips (30Hz tops)

Ahhh....the life of an engineer. We are provided with choices -- none of them ideal -- and from them devise the optimum solution.

 

Ahhh....the life of an engineer. We are provided with choices -- none of them ideal -- and from them devise the optimum solution.

That pretty much applies to my personal life as well...