LDO efficiency and GPIO bus capacitance calculations

Thread Starter

Muhammad Salleh

Joined Oct 5, 2018
34
Hi guys! For my project, i was tasked to do up a justification for a previous engineers design. Upon obtaining the voltage requirements,
upload_2018-10-26_11-50-41.png
i was wondering if i could calculate the power dissipation with regards to the
upload_2018-10-26_11-51-47.png
and therefore calculate the thermal effects determine if it satisfies the board specifications. Can i calculate the output voltage done, instead of the formula, by doing a summation of the power utilised by each component within the circuit?
 

Thread Starter

Muhammad Salleh

Joined Oct 5, 2018
34
Additionally, I also was looking at his(or her) schematic,(the engineer is not around anymore and left no documents), and i saw he used a 4.7Kohm resistor a his choice for his pull-up resistor for his I/O expander, PCA9557. Utilizing fast mode, the values used for the formula are as shown,

upload_2018-10-26_11-55-37.png

Can i ask if the calculations are correct? or if i am missing something? because from his schematic it seems that the clock lines are connected in such a way and the capacitors in parallel are much bigger than the threshold itself.

upload_2018-10-26_11-56-51.png

Once again, thank you for the advice.
 
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