Hello, I have been frustrated trying to fix my problem for a few days now and I have nowhere else to look for help, but here. I am using LTSpice to simulate a 3 bit shift register that has to be made using only inverters and T gates to create the D latches. So far I have made the clock pulse using a 555 IC and 1 latch D. The thing is that when I try to plot the functioning of my circuit, the T gate is not doing what it is supposed to do. Attached you will find a sketch made by hand of my design and the circuit. Here is the problem: as far as I know the T gate are like mirrors, pmos drain has to be connected to nmos drain and so son. For some reason LtSpice doesnt like this I was forced to play with the differents drain-source combinations until I get something logical. As you can see, when clk is 5 volts (logic 1) the first T gate will turn on and conduct what is in D to the inverters (works OK). Now, when clk is 0 it should disable the first T gate and enable the second and this will enable the data to stay "stored" between the inverters and the second T gate (doesnt work). I now this design in theory is correct, but I am just trying to figure out what I am not doing right. Maybe LTSpice is buggy? (I have tried to install it again). I have literally no idea what is going on. If you need more information I can be more than happy to provide it. As you can see you will not see the output of the second T gate connected to the first one. This was me trying to debug. It was previously connected and still didnt work. Thanks!