Hello, I have been frustrated trying to fix my problem for a few days now and I have nowhere else to look for help, but here. I am using LTSpice to simulate a 3 bit shift register that has to be made using only inverters and T gates to create the D latches. So far I have made the clock pulse using a 555 IC and 1 latch D. The thing is that when I try to plot the functioning of my circuit, the T gate is not doing what it is supposed to do. Attached you will find a sketch made by hand of my design and the circuit. Here is the problem: as far as I know the T gate are like mirrors, pmos drain has to be connected to nmos drain and so son. For some reason LtSpice doesnt like this I was forced to play with the differents drain-source combinations until I get something logical. As you can see, when clk is 5 volts (logic 1) the first T gate will turn on and conduct what is in D to the inverters (works OK). Now, when clk is 0 it should disable the first T gate and enable the second and this will enable the data to stay "stored" between the inverters and the second T gate (doesnt work). I now this design in theory is correct, but I am just trying to figure out what I am not doing right. Maybe LTSpice is buggy? (I have tried to install it again). I have literally no idea what is going on. If you need more information I can be more than happy to provide it. As you can see you will not see the output of the second T gate connected to the first one. This was me trying to debug. It was previously connected and still didnt work. Thanks!

 

You cannot use the three-pin symbol "nmos" (like the one you link to a 2n7000) that has the substrate tied to source for a transmission gate. You must use a true CMOS four pin component that has drain, source, gate and substrate brought out separately, because in a transmission gate, the substrate must be tied to VSS or VDD for an NMOS or PMOS, respectively.

Actually, you should be using the four pin component to simulate any transistor found inside a CMOS IC, including the inverters...

The four pin symbol is there in the standard symbols list:



You will have to come up with a .model that behaves like the tiny transistors found inside a real CMOS IC; the 2n7000 is not that... The default, built-in .model statements "NMOS" and "CMOS" are closer to what might exist inside a CMOS IC than linking to one of the real store-bought FETs in the standard parts library.

Why are you using the 555? If you need a clock source to test your circuit, why not just use a Pulse Voltage source?

 

Hm, I understand. So I should connect the substrate of the NMOS to 5 volts and the PMOS to ground?

 

Hm, I understand. So I should connect the substrate of the NMOS to 5 volts and the PMOS to ground?

How does your CMOS process work?

 

I am using the 555 because it is specified as a requirement. This simulation will be breadboarded in the future. All I am trying to accomplish with my design is when the clock is high, to turn on a led on the output of the T Gate (see the circuit) and when the clock is 0, the first T gates turns off and the second one turns on and this second T gate "stores" the voltage between the inverters until the clock is high again. After this I have to come up with some sort of delay mechanism to be able to implement the full 3 bit shift register with the 3 D latches. I have been stuck on this for a while.

Please see the attachment.



I tried you solution, it is not working. Actually is even worse, because the output of the T Gate now drops to around 1.2V


The FINAL project will not be simulated. I have to actually buy the components and mount it, but I want to be sure because I do not want to waste money if my design is not correct. Any help is sure appreciated.

 

Where are you going to buy P and N Fets with all four pins brought out? These exist inside CMOS process in an IC but usually not available off the shelf.

Why do you think that the tiny transistors represented by the intrinsic PMOS and NMOS models can drive a LED and a 1K resistor which takes mA of current to drive?

You obviously have no idea of the I vs V curve of the intrinsic PMOS and NMOS LTSpice devices. They are tiny; they can only supply uA of current...

 

Man, to be honest I have no idea. I am no electrical engineer. I am just trying to research and self study this up. This is a final project I must complete. I am learning as I go. The resistance I chose was just temporary. I dont even know where I can buy that, I am just trying to design this first, get approval from proffesor and buy the components later. That is exactly why I am here in these forums, because I am no expert. I am a Computer Engineer. Any help is appreciated it. I have spent many many hours trying to figure out this one way or another.

Anyways, my proffesor suggested me to use T gates in order to make the switches. I already simulated this in logic circuits (I am an expert in this area) and it was quite easy (using mux's). The things is that the requirements dont let you use gates or other IC (only the 555 timer) so I have to force my way using transistors to achieve the final full project. If you just can point me in the right direction of making just one latch functioning properly in LTSpice I will be extremely grateful. I can then replicate the knowledge for the other two latches and maybe in the future have the full 3 big shift register.

 

HI

Geez,,,I don't understand why you have to use a trans gate when their really not available.
You can "sim em",,,,but you can't "get em"...

Anyhow...Just use a 555 timer IC and a shift register IC.
Or, if you can't use a shift register IC, use CD4013B D Flip flops to build a shift register.

 

Here is a running LTSpice simulation of a D-Latch made out of the kind of complementary P and N transistors that exist only inside a CMOS IC. You will not be able to actually build this unless you have access to a CMOS fab, through MOSIS or otherwise...

To make this behave properly, I had to create two transistor models; one for the N and the other for the P transistor. The default model value of the threshold voltage Vto is 0V, and that did not simulate properly. The models I created set the threshold voltage of both the N and P transistors to be 2V and -2V, respectively, which is appropriate for a 5V CMOS process. The .model statements are shown in the schematic, and the model names "N" and "P" were substituted for the default names in the nmos4 and pmos4 symbols... This causes the D-latch to behave as you would expect, as you can see in the plots.

I suggest you read the LTSpice Help file, under:
LTspice IV/LTspice/Circuit Elements/M. MOSFET
to see how I created the .model statement to set the thresholds of the N and P.

 

Thank you very much for all you help. I still do not know why they stress out that I cannot use IC which is a lot easier. I will show the new design to see what he can recommend and where to buy that kind of NMOS and PMOS. If you say it is unlikely to find that, that is not a good sign.

Thanks again, you have been a lot of help.