hi,
For lowest current consumption FET's are the best solution.
Once the bistable FET's are wired into the circuit I would not expect ESD to be a problem.
Also the circuit already has two MOSFET devices.

I suppose the unit is going to be electrically shielded.?

E

EDIT:

Could you say how this project is going to be used.??

Hi Eric,

Do you recommend me any FET? Best FET candidate?

Thanks!
Cheers,
Isidoro

 

hi Isi,
The 2N7000 or 2N7002 as used in the circuit of post #28 would be my choice.
E

 

hi Isi,
The 2N7000 or 2N7002 as used in the circuit of post #28 would be my choice.
E

Hi @ericgibbs ,
You are right, sorry for that.
I do not have that component in my library; Do you know where I could download it?
Thanks!
Cheers,

 

Hi Isi,
Join the free Yahoo group
https://groups.yahoo.com/neo/groups/LTspice/files

Eric

 

LTspice modules and library, you could download them directly, no needs to do any registration.
http://ltwiki.org/?title=LTspiceIV-library_Library_Listing_Expanded

 

Thanks!
@ericgibbs and @ScottWang

 

Hello,

I have replaced the BJTs for FETs, but if I check the current through them and through resistors R9 & R10 is higher with FETs than with BJTs (for ON and OFF states)

Maybe, I am using the wrong figures, sorry in advance for that and thank you for your help.

Regards,

 

hi Isi,
You have not changed the resistors to the values shown in post #28.
E

 

Isidoro,
Did my circuit (post #40) not work for you?

 

Hello,

@EM Fields , I see that you deleted the post you mention on monday.

Bertus

 

Hello,

@EM Fields , I see that you deleted the post you mention on monday.

Bertus

Oops... I meant #40, so I went back and edited out my error. Thanks for the catch.

 

Oops... I meant #40, so I went back and edited out my error. Thanks for the catch.

@EM Fields
Yes! It works as expected, thanks for it!
Now I am trying to understand how it works, the flow of the currents and so on.

Cheers,

 

@EM Fields
Yes! It works as expected, thanks for it!
Now I am trying to understand how it works, the flow of the currents and so on.Cheers,

Would you like a circuit description?

 

Would you like a circuit description?

Morning @EM Fields!
Yes, please. That would be great and it will help me a lot.
Thanks!

 

hi Isi,
To cover your concerns regarding noise immunity, the final build should have capacitor decoupling on the power rails.
Eric

 

Morning @EM Fields!
Yes, please. That would be great and it will help me a lot.
Thanks!

OK.
When power is first turned on, the junction of R3C3 will be low, and this low will cause the output of U1A to go high. That high will be inverted by U1B, and the low from U1B's output will cause the output of U1D to go high, which will turn Q1 (an enhancement mode P-channel MOSFET) OFF, disconnecting power from the load, R6.
U1C and U1D comprise an R-S latch, and when C3 charges up and U1B OUT goes high, U1D out will remain high until S1 is made.

When S1 is made, the resultant low-going edge at the junction of R1C1 will be differentiated by R2C1 and a short low-going spike will appear at the R2C1 junction and at PLSON\, which will change the state of the latch and drive RUN\ low, which will turn Q1 ON, connecting power to R6.
When S1 is released, the latch will be unaffected and Q1 will continue to be turned ON until S2 is made.

When S2 is made, the resultant low-going edge at the junction of R4C2 will be differentiated by R5C2 and a short low-going spike will appear at the R5C2 junction and at PLSOFF\, which will change the state of the latch and drive RUN\ high, which will turn Q1 OFF, disconnecting power to R6.
When S2 is released, the latch will be unaffected and Q1 will continue to be turned OFF until S1 is made.

 

OK.
When power is first turned on, the junction of R3C3 will be low, and this low will cause the output of U1A to go high. That high will be inverted by U1B, and the low from U1B's output will cause the output of U1D to go high, which will turn Q1 (an enhancement mode P-channel MOSFET) OFF, disconnecting power from the load, R6.
U1C and U1D comprise an R-S latch, and when C3 charges up and U1B OUT goes high, U1D out will remain high until S1 is made.

When S1 is made, the resultant low-going edge at the junction of R1C1 will be differentiated by R2C1 and a short low-going spike will appear at the R2C1 junction and at PLSON\, which will change the state of the latch and drive RUN\ low, which will turn Q1 ON, connecting power to R6.
When S1 is released, the latch will be unaffected and Q1 will continue to be turned ON until S2 is made.

When S2 is made, the resultant low-going edge at the junction of R4C2 will be differentiated by R5C2 and a short low-going spike will appear at the R5C2 junction and at PLSOFF\, which will change the state of the latch and drive RUN\ high, which will turn Q1 OFF, disconnecting power to R6.
When S2 is released, the latch will be unaffected and Q1 will continue to be turned OFF until S1 is made.

View attachment 122009

Thank you very much for your time!
@EM Fields

 

Hello all,

I am not 100% sure about the circuit, due to the initial state looks a bit arbitrary (ON or OFF).
Is there any way that I could force the initial state to be OFF, yes or yes 100%?

Thanks!
Cheers,

 

hi Iso,
There is a method to do an initial power up Reset, if E M Fields does not get back to you, I will post.
E

 

Hello all,

I am not 100% sure about the circuit, due to the initial state looks a bit arbitrary (ON or OFF).
Is there any way that I could force the initial state to be OFF, yes or yes 100%?

Thanks!
Cheers,

The circuit provided by EMFields already has power-on reset behavior. He described how it works in the first paragraph of his post. Basically, the capacitor C3 initially holds one of the inputs of U1A LO, which forces the latch to be SET (and, because of the inverting nature of the PFET switch, forces it to be OFF).

By changing the values of R3 and C3 you can control how long this initial reset pulse lasts. The given values give a pulse that is approximately 1 ms. You want it to last long enough so that the power supplies and all of the circuitry has time to stabilize.