# Lab questions

#### Hunter Neumann

Joined Aug 24, 2015
53
I have no clue how to implement an adder using two xor gates and a minimal number of 2 input Nand and Nor Gates. All we have learned about adders is that it has 3 inputs and produces 2 outputs (carry out and sum). I get that and how to make the truth table for it but idk what my professor is trying to get me to do. If anyone can explain that would be great.

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#### WBahn

Joined Mar 31, 2012
25,566
Well, the first thing is to make the truth table for each of the outputs. Until you do that and show us the results, we can't go much further.

#### Hunter Neumann

Joined Aug 24, 2015
53
Well, the first thing is to make the truth table for each of the outputs. Until you do that and show us the results, we can't go much further.

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#### WBahn

Joined Mar 31, 2012
25,566
Good.

So now focus on the 'sum' output. See if you can figure out how to implement that using two XOR gates.

#### Hunter Neumann

Joined Aug 24, 2015
53
I am not sure how to with two, I got the sum right by using one xor gate

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#### Hunter Neumann

Joined Aug 24, 2015
53
Good.

So now focus on the 'sum' output. See if you can figure out how to implement that using two XOR gates.
Is this right? could I simplify it further by taking out one of the nand gates and one of the nor?

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#### WBahn

Joined Mar 31, 2012
25,566
I am not sure how to with two, I got the sum right by using one xor gate
Do you REALLY need 1.5 MB files?

The description implies two 2-input XOR gates. If 3-input XOR gates are fair game, then what you did is fine as far as it goes, but by using two 2-input XOR gates you can reduce the number of 2-input NAND/NOR gates you need for the carry output.

#### Hunter Neumann

Joined Aug 24, 2015
53
Do you REALLY need 1.5 MB files?

The description implies two 2-input XOR gates. If 3-input XOR gates are fair game, then what you did is fine as far as it goes, but by using two 2-input XOR gates you can reduce the number of 2-input NAND/NOR gates you need for the carry output.
Does this look right using two input gates? could I simplify them any further?

#### djsfantasi

Joined Apr 11, 2010
6,338
Yes.

The 2 NOR gates are equivalent to an OR gate. Look up the equivalent of an OR gate using NAND gates. Redraw the circuit, and several simplifications will be apparent.

#### Hunter Neumann

Joined Aug 24, 2015
53
Yes.

The 2 NOR gates are equivalent to an OR gate. Look up the equivalent of an OR gate using NAND gates. Redraw the circuit, and several simplifications will be apparent.
what would be the most simplified way to do it using nor and nand gates? would I use them both? I'm not sure if my professor wants me to use both or just one. Im not good at simplifying them. Thats the only issue I have had in this class.

#### djsfantasi

Joined Apr 11, 2010
6,338
what would be the most simplified way to do it using nor and nand gates? would I use them both? I'm not sure if my professor wants me to use both or just one. Im not good at simplifying them. Thats the only issue I have had in this class.
In this case, have you done what I suggested? It should be quite obvious how to simplify from the schematic that results.

#### WBahn

Joined Mar 31, 2012
25,566
The instructions indicate that you can use a combination of both of them if you want, but the goal is to minimize the total number of them.

HINT: It can be done using three of these gates in addition to the two XOR gates.

#### WBahn

Joined Mar 31, 2012
25,566
Yes.

The 2 NOR gates are equivalent to an OR gate. Look up the equivalent of an OR gate using NAND gates. Redraw the circuit, and several simplifications will be apparent.
Keep in mind that the constraints of the problem allow him to use two XOR gates plus any number of addition 2-input NAND or NOR gates (with the goal to minimize that number).

#### Hunter Neumann

Joined Aug 24, 2015
53
Keep in mind that the constraints of the problem allow him to use two XOR gates plus any number of addition 2-input NAND or NOR gates (with the goal to minimize that number).
Is this right? I really just used trial and error. I don't know how you guys can figure that stuff out so quickly

#### djsfantasi

Joined Apr 11, 2010
6,338

#### djsfantasi

Joined Apr 11, 2010
6,338
Keep in mind that the constraints of the problem allow him to use two XOR gates plus any number of addition 2-input NAND or NOR gates (with the goal to minimize that number).
WBahn - I had that in mind.

#### WBahn

Joined Mar 31, 2012
25,566
WBahn - I had that in mind.
Oh -- I thought you were thinking along the lines of reducing the NAND followed by the NAND with tied inputs down to an AND. But I see what you are focusing on -- the rightmost four gates and reducing that to a NAND.

#### WBahn

Joined Mar 31, 2012
25,566
View attachment 93269

Is this right? I really just used trial and error. I don't know how you guys can figure that stuff out so quickly
Yes.

With experience and practice you learn how to spot things. One very useful technique is known as "bubble logic" where you basically apply DeMorgan's theorem graphically to the logic symbols by adding/moving inversion bubbles around and swapping OR with AND (or vice-versa) while adding bubbles to all inputs/outputs. If you do that to the left NOR gate, it becomes and AND gate with bubbles at the two inputs and no bubble at the output (the new bubble cancels the bubble that was already there). The final NOR gate is just an inverter and so it becomes a bubble at the output of the NOR gate. The bubbles at the inputs cancel the two NAND gates that are to the left of them, since each of those is just an invertor. You thereby replace the four right-most gates with a single NAND gate.

EDIT: Fix typo: simples -> symbols

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