JFET design problem, solve for Rd using Gain

Thread Starter

tonym1069

Joined Aug 17, 2010
6
Hello All,
This is an online electronics 1 class. I only talk to teacher through email and he is cryptic. I am really frustrated. I should not be getting a negative solution for resistor RD. My Professor says the value highlighted in yellow should be under 50. The only way I can see to make this happen is to change gmo from 6.4*10^-3 or 6.4mS to just 6.4 S. I looked in the book at an example spec sheet for a Fairchild 2N5457 N-channel Amp. They list gos (output conductance as a value between 10 -50 micro mhos. so in this problem is the value of Yos = 20 micro mS or 20*10^-6 mS, where I was interpreting Yos as 20*10^-3 S.
Thank you for any help, trying to do this with work, kids, wife and everything else is hard.
Problem 4 Capture.PNG
 

Jony130

Joined Feb 17, 2009
5,333
Change Yos to 20μS and repeat the calculations. RD will be around 1.9kΩ. For Yos =20mS is impossible to get any gain from this circuit Av_max = 6.4mS/20mS = 0.32 [V/V]
 

Thread Starter

tonym1069

Joined Aug 17, 2010
6
Change Yos to 20μS and repeat the calculations. RD will be around 1.9kΩ. For Yos =20mS is impossible to get any gain from this circuit Av_max = 6.4mS/20mS = 0.32 [V/V]
Thank you, I had gone down this road because the textbook gave all problems with a Yos in the microamp range. The textbook had a section on design problems that is why I solved the problem the way I did. I thought maybe that you might run into this problem when designing JFET amplifiers but now I think it was a typo in the assignment. Thank you for the help.
Cheers,
Tony
 
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