J-K fliflop clock dutycycle.

Discussion in 'The Projects Forum' started by imbaine13, Mar 7, 2015.

  1. imbaine13

    Thread Starter Member

    Oct 6, 2013
    Hello everyone,

    I really need your help here. I have been reading up on logic gates, latches and flipflops, however there's a little thing that is still confusing about the J-K flipflop. I know that idealy, if both the J and K inputs are held high and the clock input strobed at some frequency, the outputs (Q and notQ) would toggle at each rising edge of the clock input (assuming a positive edge triggered flipflop); but what would happen if the clock signal is not strobed, but rather a square wave with a 50% dutycycle of very low frequncy (or even the clock input just held HIGH!)? Wouldn't the outputs both be unstable, and therefore oscillate rapidly during the HIGH state of clock input?
    I'm not sure if there's circuitry in the dedicated J-K flipflop chips to prevent this kind of thing happening, but suppose I were to build one from descrete logic gates. Would it oscillate like I described? I'm mainly interested in wheather the flipflop has some kind of natural tendency to reject unstrobed clock inputs.
    The total delay time from the input of the AND gates to the output of the NOR gates may be as little as 3.552x10^-8 seconds, which means if the clock signal goes HIGH when output Q is high (flipflop SET), that would be the maximum amount of time we would want the clock signal to remain high (before Q and not Q change states) otherwise the flipflop would reset and set over and over again because the feedback from the output would reach the inputs of the AND gates faster than the clock is switching.

    Long story short, what would the recommended high time of the clock input signal be for a J-K flipflop?

    I'm trying to build a bipolar stepper motor driver using a 2 bit synchronous counter (implemented by J-K flipflops) whose output if fed to a decoder circuit. The decoder will drive 2 H-bridges using high power bjt's (TIP41 and TIP42 to be exact or darlington pairs). I'm planning on suppling the counter clock with pulses from a 555 timer.

    I'm not sure if you get me, but I hope the sketch I attached will clear things out.

    Appreciate you time.
  2. Marcus2012


    Feb 22, 2015
    Hi :)

    If you are using an astable 555 output for the clock input then it doesn't matter too much what the duty cycle is. I would say just try and get as close to 50% as possible or a little higher if you cant just to get as well define a period as possible for the JK FF input. The reason I say the duty cycle does matter too much is that the JK FF in toggle mode will inherently convert the duty cycle to 50% for its outputs anyway regardless of the input duty cycle. The JK FF I'm currently using states it has a max clock frequency of 30Mhz but of course any output from that would be half.

    Hope that helps :D

    Here's a good astable 555 calculator that gives duty cycles and commonly available R and C values.

    555 Astable calculator House of Jeff

    EDIT: to answer you question about a constant HIGH or LOW clock input. The JK will do nothing, it will only "flip" (transition to high output) or "flop" (transition to low output) when it detects a transition from low to high (in positive edge) on the clock input. notQ will be a direct complement of Q output.
    Last edited: Mar 7, 2015
  3. crutschow


    Mar 14, 2008
    Most IC flip-flops are edge-triggered and it makes no difference how long the clock stays high or low. The FF output will stay at the state generated during the last clock rising edge (for positive edge triggered flip-flops) until the next rising edge. (With the limit that the high or low time can be no shorter than the minimum required for proper FF operation of the particular FF being used, as stated in the data sheet).
  4. AnalogKid

    AAC Fanatic!

    Aug 1, 2013
    For any edge-triggered flip flop, no matter what type or which edge (positive-going or negative-going) the outputs are stable at all times. That is, they do not change state for any reason except the occurrence of a clock edge, and then change state only once with each edge. A JK flip flop is relatively complex internally, and that complexity gets you stability. It can sit forever with theh clock signal in either the high or low atate and the outputs will not change, even if the J and K inputs are changing. No clock *edge*, no output change.