I am confused regarding this. After having read from several sources, I have come across the following points:
1. Race condition exists in JK flip flops when clock pulse goes off before the propagation delay
2. Race condition does not occur in JK flip flops if they are edge triggered
3. Race condition does not occur in JK flip flops if their clock pulses have high frequency.

But none of the above points have any proper explanations. When I learnt JK flip flops, I always learnt them to be negative edge triggered flip flops and I didn't even know they were other types of JK flip flops. I even practised JK, T, D waveforms by changing the output state when the clock pulse was falling (negative edge). So point 2 is very vague.
Plus I also learnt that SR flips have a race condition at 1,1 and JK flip flops are an improvement of this so that at this input 1,1 Q is the complement of the previous state thus avoiding an indeterminate output state. So I am surprised that this improved flip flop is even expected to have the same race condition (like SR) at 1,1

 

If you think about it, the fact that you have setup and hold time requirements is because any operation that violates them creates the potential for a critical race condition.

In general, race conditions are as much about implementation as they are about functionality. The details of the logic design as well as the routing of the signals can produce races, both critical and non-critical. More than anything else, this is what makes asynchronous logic, for all of it's significant advantages, something that many design guidelines absolutely forbid unless there is an extremely good and justifiable reason (and extremely good and justifiable reasons DO exist, but they are the exception rather than the rule).